Apparatus and method for clock generation

Abstract

A clock and data recovery (CDR) system may use one or more clock signals in sync with recovered data rate. By accumulating a dithering tuning counter value at a data oversampling rate, a plurality of single bit signals at multiples of the recovered data rate and in sync with the recovered data rate can be accurately generated while utilizing the full range of the accumulator. This plurality of clock signals can be used in various modules in the CDR system and other modules in a transceiver system incorporating the CDR system.

What is claimed is: 
     
       1. An apparatus comprising:
 a dithering circuit configured to generate a tuning word based on a first clock frequency from a first clock signal, wherein the first clock signal is generated from a clock and data recovery (CDR) system, wherein the tuning word comprises a multi-bit word, wherein the dithering circuit is configured to repeatedly switch between a first value and a second value to generate the tuning word, and wherein the dithering circuit is configured to switch at the first clock frequency from the first clock signal; and 
 an accumulator configured to accumulate the tuning word with a previous accumulator output value to generate a new accumulator output value at a second clock frequency from a second clock signal. 
 
     
     
       2. The apparatus of  claim 1 , further comprising at least one logic circuit configured to generate a plurality of clock signals respectively based on a plurality of different bit values of the new accumulator output value. 
     
     
       3. The apparatus of  claim 2 , further comprising a transmitter module and/or a receiver module configured to receive the plurality of clock signals. 
     
     
       4. The apparatus of  claim 1 , further comprising a resetting circuit configured to reset the accumulator based in part on the new accumulator output value. 
     
     
       5. The apparatus of  claim 1 , wherein the tuning word is generated based in part on an effective data rate value, and wherein the effective data rate value is generated by a processor based on the data rate of the CDR system and a scaling factor. 
     
     
       6. The apparatus of  claim 5 , wherein the CDR system comprises one or more data rate correcting modules configured to adjust the data rate. 
     
     
       7. The apparatus of  claim 1 , wherein the new accumulator output value is further based on a programmable modulus. 
     
     
       8. The apparatus of  claim 1 , wherein the second clock signal is generated from a crystal oscillator. 
     
     
       9. A method for clock generation comprising:
 generating a first clock signal; 
 receiving a second clock signal; 
 switching repeatedly between a first value and a second value to generate a tuning word, wherein the switching occurs at a first clock frequency from the first clock signal, wherein the tuning word comprises a multi-bit word; and 
 accumulating the tuning word to a previous accumulator output value to generate a new accumulator output value at a second clock frequency from the second clock signal. 
 
     
     
       10. The method of  claim 9 , further comprising generating a plurality of clock signals respectively based on a plurality of different bit values of the new accumulator output value. 
     
     
       11. The method of  claim 10 , further comprising sending the plurality of clock signals to a transmitter module and/or a receiver module. 
     
     
       12. The method of  claim 9 , further comprising resetting the accumulator based in part on the new accumulator output value. 
     
     
       13. The method of  claim 9 , wherein the tuning word is generated based in part on an effective data rate value, and wherein the effective data rate value is generated by a processor based on a data rate of a clock and data recovery (CDR) system and a scaling factor. 
     
     
       14. The method of  claim 13 , further comprising adjusting the data rate with one or more data rate correcting modules. 
     
     
       15. The method of  claim 9 , wherein the new accumulator output value is further based on a programmable modulus. 
     
     
       16. An apparatus for clock generation, the apparatus comprising:
 a means for generating a first clock signal; 
 a means for switching repeatedly between a first value and a second value to generate a tuning word, wherein the switching occurs at a first clock frequency from the first clock signal, wherein the tuning word comprises a multi-bit word; and 
 a means for accumulating the tuning word to a previous accumulator output value to generate a new accumulator output value at a second clock frequency from a second clock signal. 
 
     
     
       17. The apparatus of  claim 16 , further comprising a means for generating a plurality of clock signals respectively based on a plurality of different bit values of the new accumulator output value. 
     
     
       18. The apparatus of  claim 16 , further comprising a means for resetting the accumulator based in part on the new accumulator output value. 
     
     
       19. The apparatus of  claim 16 , wherein the tuning word is generated based in part on an effective data rate value, and wherein the effective data rate value is generated by a processor based on a data rate of a clock and data recovery (CDR) system and a scaling factor. 
     
     
       20. The apparatus of  claim 19 , further comprising a means for adjusting the data rate with one or more data rate correcting modules. 
     
     
       21. The apparatus of  claim 16 , wherein the new accumulator output value is further based on a programmable modulus.