Pipelined cascaded digital signal processing structures and methods

Abstract

Circuitry operating under a floating-point mode or a fixed-point mode includes a first circuit accepting a first data input and generating a first data output. The first circuit includes a first arithmetic element accepting the first data input, a plurality of pipeline registers disposed in connection with the first arithmetic element, and a cascade register that outputs the first data output. The circuitry further includes a second circuit accepting a second data input and generating a second data output. The second circuit is cascaded to the first circuit such that the first data output is connected to the second data input via the cascade register. The cascade register is selectively bypassed when the first circuit is operated under the fixed-point mode.

What is claimed is: 
     
       1. Circuitry operating under a floating-point mode or a fixed-point mode, said circuitry comprising:
 a first circuit accepting a first data input and generating a first data output, the first circuit including:
 a first arithmetic element accepting the first data input, 
 a plurality of pipeline registers disposed in connection with the first arithmetic element, and 
 a cascade register that outputs the first data output; and 
 
 a second circuit accepting a second data input and generating a second data output, wherein:
 the second circuit is cascaded to the first circuit such that the first data output is connected to the second data input via the cascade register, and 
 the cascade register is selectively bypassed when the first circuit is operated under the fixed-point mode. 
 
 
     
     
       2. The circuitry of  claim 1 , wherein the first arithmetic element includes a multiplier that supports floating-point multiplication. 
     
     
       3. The circuitry of  claim 1 , wherein the second circuit includes a second arithmetic element that supports floating-point operation, and wherein
 the second arithmetic element accepts the second data input via the cascade register and generates the second data output. 
 
     
     
       4. The circuitry of  claim 1 , wherein the cascade register and a balancing register are used when the first circuit and the second circuit are operated under the floating-point mode. 
     
     
       5. The circuitry of  claim 1 , wherein a pipeline register from the plurality of pipeline registers is selectively bypassed when the cascade register is used. 
     
     
       6. The circuitry of  claim 1 , wherein the second circuit further includes a second arithmetic element, a third arithmetic element, a second plurality of pipeline registers disposed with the second arithmetic element, and a plurality of input balancing registers, and wherein the second arithmetic element accepts the second data input. 
     
     
       7. The circuitry of  claim 6 , wherein a last register of the second plurality of pipeline registers is connected to an input balancing register from the plurality of input balancing registers, and
 data from the input balancing register is fed into the second arithmetic element. 
 
     
     
       8. The circuitry of  claim 1 , further comprising:
 a third circuit accepting a third data input and generating a third data output. 
 
     
     
       9. A method of operating cascaded circuitry, comprising:
 receiving, via a plurality of input registers within a first circuit, a data input signal, wherein 
 the first circuit includes:
 a first arithmetic element that supports floating-point operation, 
 a plurality of pipeline registers that pipeline an operation of the first arithmetic element, and 
 a cascade register that is connected to a second circuit; 
 
 receiving, from a processor, a first command signal to use the cascade register; and 
 in response to the first command signal:
 selectively bypassing an input register from the plurality of input registers, or a pipeline register from the plurality of pipeline registers to compensate for a delay from the cascade register, and 
 transmitting, via the cascade register, an interblock data signal from the first circuit to the second circuit. 
 
 
     
     
       10. The method of  claim 9 , further comprising:
 receiving, from the processor, a second command signal to bypass the cascade register; and 
 in response to the second command signal,
 transmitting the interblock data signal from the first circuit to the second circuit without passing through the cascade register. 
 
 
     
     
       11. The method of  claim 10 , wherein:
 the processor sends the first command signal when the data input signal has a floating-point format; and 
 the processor sends the second command signal when the data input signal has a fixed-point format.