US9672877B2ActiveUtilityA1

Interfaces and die packages, and apparatuses including the same

Assignee: MICRON TECHNOLOGY INCPriority: Oct 18, 2011Filed: Oct 3, 2016Granted: Jun 6, 2017
Est. expiryOct 18, 2031(~5.2 yrs left)· nominal 20-yr term from priority
Inventors:Oh Seung Min
C23C 16/4585G11C 7/1012G11C 2213/71G11C 7/1069G11C 7/10G11C 7/1093G11C 5/02G11C 7/1084C23C 14/50G11C 7/1066C23C 16/042C23C 14/042H10P 72/3222H10P 72/3202H10P 72/78H10P 72/53H10P 72/18H10P 72/17H10W 90/754H10W 90/752H10W 90/734H10W 90/732H10W 90/24H10W 72/9445H10W 72/5445H10W 72/932H10W 72/884H10W 72/59H10W 70/63H10W 90/00H10W 72/00H10P 72/57H01L 2224/48227H01L 24/73H01L 2924/00014H01L 2224/48225H01L 2224/05553H01L 2924/1301H01L 2224/05554H01L 2224/45099H01L 2224/48145H01L 2224/32225H01L 2224/49175H01L 25/18H01L 2224/32145H01L 2224/73265H01L 2225/06506H01L 25/0657H01L 2225/06562H01L 2224/48106H01L 2924/1434H01L 2224/06155H01L 23/48H01L 2924/15192H01L 2924/00012H01L 24/48H01L 2924/00H01L 2224/04042H01L 2225/0651H01L 2224/48147H10F 71/00
83
PatentIndex Score
2
Cited by
10
References
9
Claims

Abstract

A memory device includes a memory die package including a plurality of memory dies, an interface device including an interface circuit, and a memory controller configured to control the interface with control data received from at least one of the plurality of memory dies. The interface device of the memory device is configured to divide and multiplex an IO channel between the memory die package and the memory controller into more than one channel using the control data receive from the at least one of the plurality of memory dies. The interface device for a memory device includes a control input buffer configured to receive an enable signal through a control pad, a first input buffer configured to receive a first data through a first IO pad in response to a first state of the enable signal, and a second input buffer configured to receive a second data through a second IO pad in response to a second state of the enable signal. The interface device further includes an input multiplexer configured to multiplex the first data and the second data to provide an input data.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
       1. An interface device, comprising:
 a control input buffer configured to receive an enable signal; 
 a first input buffer configured to receive first data and provide first input data; 
 a second input buffer configured to receive second data and provide second input data; and 
 an input multiplexer configured to multiplex the first input data and the second input data to provide integrated data in response to the enable signal. 
 
     
     
       2. The interface device of  claim 1 , wherein the device is configured to alternate receiving the first data through the first input buffer and receiving the second data through the second input buffer. 
     
     
       3. The interface device of  claim 1 , further comprising:
 a delay unit configured to provide a delay to the integrated data; and 
 a latch unit configured to store the delayed integrated data. 
 
     
     
       4. The interface device of  claim 1 , wherein the first input buffer is configured to receive a first die enable signal and to provide the first input data in response to receiving the first die enable signal, and the second input buffer is configured to receive a second die enable signal and to provide the second input data in response to receiving the second die enable signal. 
     
     
       5. The interface device of  claim 1 , further comprising:
 a first input/output (IO) pad configured to receive the first data from a first group of dice in die package; and 
 a second IO pad configured to receive the second data from a second group of dice in the die package. 
 
     
     
       6. A memory device, comprising:
 a plurality of memory dice; and 
 an interface device having
 a control input buffer configured to receive an enable signal through a control pad from a first group of the plurality of memory dice, each of the first group of memory dice being coupled to the control pad, 
 a first input buffer configured to receive first data through a first input/output (IO) pad from the first group of memory dice, each of the first group of memory dice being coupled to the first IO pad, 
 a second input buffer configured to receive second data through a second IO pad from a second group of the plurality of memory dice, each of the second group of memory dice being coupled to the second IO pad, and 
 an input multiplexer configured to multiplex the first data and the second data to provide integrated data in response to the enable signal. 
 
 
     
     
       7. A memory device, comprising:
 a plurality of memory dice; and 
 an interface device having
 an output multiplexer configured to divide the output data to provide first data and second data in response to an external control signal, the output multiplexer being further configured to provide a first control signal and a second control signal; 
 a first pre-driving circuit configured to provide a first pull-up signal and a first pull-down signal in response to the first data and the first control signal; 
 a first output buffer configured to provide a first output data in response to the first pull-up signal and the first pull-down signal through a first input/output (IO) pad coupled to a first group of the plurality of memory dice; 
 a second pre-driving circuit configured to provide a second pull-up signal and a second pull-down signal in response to the second data and the second control signal; and 
 a second output buffer configured to provide a second output data in response to the second pull-up signal and the second pull-down signal through a second IO pad coupled to a second group of the plurality of memory dice. 
 
 
     
     
       8. A memory apparatus, comprising:
 a controller interfaced to a plurality of dice divided into groups of dice; and 
 respective input/output (IO) buses to couple the controller to each of the groups of dice, each IO bus being decoupled from other groups of dice, the memory apparatus being configured to multiplex information exchanged with selected ones of the groups of dice on the respective IO bus in response to a control signal. 
 
     
     
       9. An interface device couplable between a controller and a plurality of groups of circuits, the interface device comprising:
 a control input buffer configured to receive an enable signal from the controller, the controller having a channel to couple with the interface device; 
 a first input buffer configured to receive first data and provide first input data; 
 a second input buffer configured to receive second data and provide second input data; and 
 an input multiplexer configured to multiplex the first input data and the second input data to provide integrated data in response to the enable signal, the input multiplexer being further configured to select one channel from a number of channels, the number of channels corresponding to a respective one of the plurality of groups of circuits, the input multiplexer to couple the selected one channel to the controller at a time.

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