US9664970B2ActiveUtilityA1

LCD panel wherein TFT units to mitigate gate signal delay are disposed opposite to the gate driver and connected to individual gate lines

Assignee: BOE TECHNOLOGY GROUP CO LTDPriority: May 31, 2013Filed: Oct 25, 2013Granted: May 30, 2017
Est. expiryMay 31, 2033(~6.8 yrs left)· nominal 20-yr term from priority
Inventors:Zheng Wang
G09G 3/3677G02F 1/13306G02F 1/136286G02F 1/1368G09G 2320/0223G09G 3/3674G09G 2310/0283G09G 2310/0286G09G 2300/0408
48
PatentIndex Score
0
Cited by
27
References
4
Claims

Abstract

Disclosed is an LCD panel. The LCD panel comprises a display area ( 13 ), and a first signal line, a second signal line . . . an N th signal line which are connected to the display area ( 13 ), wherein the LCD panel further comprises a TFT area ( 14 ). One side of the display area ( 13 ) is provided with a first signal output port, a second signal output port . . . an N th signal output port. The TFT area ( 13 ) comprises a first TFT unit, a second TFT unit . . . an (N+1) th TFT unit; and both the first TFT unit and the (N+1) th TFT unit comprise one TFT, and the second TFT unit to the N th TFT unit respectively comprise two TFTs, i.e. a first TFT and a second TFT. Further disclosed is a display device. By adopting the LCD panel, a circuit of a gate driver can be made to be more simple and occupy less space on the basis of not changing gate signal characteristics.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
       1. A liquid crystal display (LCD) panel comprising: a display area, and a first signal line, a second signal line through an N th  signal line which are connected to the display area, wherein the LCD panel further comprises a thin film transistor (TFT) area; a first signal output port, a second signal output port through an N th  signal output port are disposed at a side of the display area; the TFT area comprises a first TFT unit, a second TFT unit through an (N+1) th  TFT unit; each of the first TFT unit and the (N+1) th  TFT unit comprises one TFT, and each of the second TFT unit through an N th  TFT unit comprises two TFTs which are a first TFT and a second TFT; wherein
 in the first TFT unit, a gate electrode of the TFT is connected to the first signal output port, and a source electrode of the TFT is connected to the first signal line; 
 in the second TFT unit, a gate electrode of the first TFT is connected to the first signal output port, a source electrode of the first TFT is connected to the second signal line, and a drain electrode of the first TFT is connected to the second signal output port, the first TFT is configured for transmitting a signal transmitted by the second signal line to the second signal output port in response to a signal of the first signal output port; and in the second TFT unit, a gate electrode of the second TFT is connected to the second signal output port, a source electrode of the second TFT is connected to the first signal line, and a drain electrode of the second TFT is connected to the first signal output port, the second TFT is configured for transmitting a signal transmitted by the first signal line to the first signal output port in response to a signal of the second signal output port; 
 in the N th  TFT unit, a gate electrode of the first TFT is connected to an (N−1) th  signal output port, a source electrode of the first TFT is connected to the N th  signal line, and a drain electrode of the first TFT is connected to the N th  signal output port; and in the N th  TFT unit, the first TFT is configured for transmitting a signal transmitted by the N th  signal line to the N th  signal output port in response to a signal of the (N−1) th  signal output port; a gate electrode of the second TFT is connected to the N th  signal output port, a source electrode of the second TFT is connected to the (N−1) th  signal line, and a drain electrode of the second TFT is connected to the (N−1) th  signal output port, the second TFT is configured for transmitting a signal transmitted by the (N−1) th  signal line to the (N−1) th  signal output port in response to a signal of the N th  signal output port; and 
 in the (N+1) th  TFT unit, a gate electrode of the TFT is connected to the N th  signal output port, and a source electrode of the TFT is connected to the N th  signal line. 
 
     
     
       2. The LCD panel according to  claim 1 , wherein the LCD panel further comprises a gate drive on array (GOA) region comprising a first GOA unit, and a second GOA unit through an N th  GOA unit; wherein
 the first GOA unit is connected to the first signal line, and is connected to the first signal output port through the display area; 
 the second GOA unit is connected to the second signal line, and is connected to the second signal output port through the display area; and 
 the N th  GOA unit is connected to the N th  signal line, and is connected to the N th  signal output port through the display area. 
 
     
     
       3. A display device comprising an LCD panel according to  claim 1 . 
     
     
       4. The display device according to  claim 3 , wherein the LCD panel further comprises a gate drive on array (GOA) region comprising a first GOA unit, and a second GOA unit through an N th  GOA unit; wherein
 the first GOA unit is connected to the first signal line, and is connected to the first signal output port through the display area; 
 the second GOA unit is connected to the second signal line, and is connected to the second signal output port through the display area; and 
 the N th  GOA unit is connected to the N th  signal line, and is connected to the N th  signal output port through the display area.

Join the waitlist — get patent alerts

Track US9664970B2 — get alerts on status changes and closely related new filings.

We store only your email — no account needed. See our privacy policy.