Testing and setting performance parameters in a semiconductor device and method therefor

Abstract

A method of determining temperature ranges and setting performance parameters in a semiconductor device that may include at least one temperature sensing circuit is disclosed. The temperature sensing circuits may be used to control various operating parameters to improve the operation of the semiconductor device over a wide temperature range. The performance parameters may be set to improve speed parameters and/or decrease current consumption over a wide range of temperature ranges.

What is claimed is: 
     
       1. A device, comprising:
 a temperature circuit that sets a plurality of temperature ranges; 
 a performance parameter table, the performance parameter table provides performance parameters based on the temperature range in which the device is operating; and 
 performance parameter adjustable circuits coupled to receive the performance parameters and test performance parameters. 
 
     
     
       2. The device of  claim 1 , further including:
 a first counter circuit coupled to provide the test performance parameters. 
 
     
     
       3. The device of  claim 2 , wherein:
 the first counter circuit is coupled to receive an increment signal, the first counter circuit incrementally changes the test performance parameters in response to the increment signal. 
 
     
     
       4. The device of  claim 3 , wherein:
 the first counter circuit is coupled to receive a reset signal, the first counter circuit resets the test performance parameters to a predetermined state in response to the reset signal. 
 
     
     
       5. The device of  claim 1 , further including:
 a plurality of multiplexer circuits, each multiplexer circuit is coupled to receive one of the performance parameters at a first multiplexer input terminal and one of the test performance parameters at a second multiplexer input terminal and provide an output at a multiplexer output terminal, the performance parameter adjustable circuits include input terminals, each input terminal of the performance parameter adjustable circuits is coupled to one of the multiplexer output terminals from the plurality of multiplexer circuits. 
 
     
     
       6. The device of  claim 5 , wherein:
 the plurality of multiplexer circuits are coupled to receive a test signal at a control terminal, each multiplexer circuit provides a low impedance path between the one of the test performance parameters and the multiplexer output terminal when the test signal has a first logic level and a high impedance path between the one of the test performance parameters and the multiplexer output terminal when the test signal has a second logic level. 
 
     
     
       7. The device of  claim 6 , wherein:
 each one of the plurality of multiplexer circuits includes
 a first pass gate having a controllable impedance path coupled between the first multiplexer input terminal and the multiplexer output terminal; and 
 a second pass gate having a controllable impedance path coupled between the second multiplexer input terminal and the multiplexer output terminal. 
 
 
     
     
       8. The device of  claim 7 , further including:
 a plurality of latch circuits, each latch circuit having a latch input terminal coupled to receive one of the performance parameters and a latch output terminal coupled to one of the second multiplexer input terminals of the plurality of multiplexers. 
 
     
     
       9. The device of  claim 8 , wherein:
 each one of the plurality of latch circuits is coupled to receive a load signal, each one of the latch circuits latches a corresponding performance parameter in response to the load signal. 
 
     
     
       10. The device of  claim 1 , wherein:
 the performance parameter adjustable circuits include subthreshold voltage operating circuits including at least one first insulated gate field effect transistor (IGFET) having a first conductivity type and a first IGFET threshold voltage, the subthreshold voltage operating circuits operate from a power supply having a potential less than the first IGFET threshold voltage. 
 
     
     
       11. The device of  claim 10 , wherein:
 the at least one first IGFET is coupled to receive a first back body bias potential having a potential determined by the performance parameters in a normal mode of operation and the test performance parameters in a test mode of operation. 
 
     
     
       12. The device of  claim 1 , wherein:
 the performance parameter adjustable circuits further include above subthreshold voltage operating circuits including at least one second IGFET having a first conductivity type and a second IGFET threshold voltage, the above subthreshold voltage operating circuits operate from a second power supply having a potential greater than the second IGFET threshold voltage. 
 
     
     
       13. The device of  claim 12 , wherein:
 the at least one second IGFET is coupled to receive a second back body bias potential having a potential determined by the performance parameters in a normal mode of operation and the test performance parameters in a test mode of operation. 
 
     
     
       14. The device of  claim 1 , wherein:
 the device is a semiconductor device. 
 
     
     
       15. The device of  claim 14 , wherein:
 the semiconductor device is a semiconductor memory device. 
 
     
     
       16. A device, comprising:
 a temperature circuit that sets a plurality of temperature ranges; 
 a performance parameter table, the performance parameter table provides performance parameters based on the temperature range in which the device is operating; and 
 performance parameter adjustable circuits coupled to receive the performance parameters from the performance parameter table; and 
 the performance parameter table is programmed with the performance parameters received externally from the device. 
 
     
     
       17. The device of  claim 16 , further including:
 a serial register coupled to serially receive externally provided performance parameters in response to a clock signal and provide in parallel the performance parameters to be programmed into the performance parameter table. 
 
     
     
       18. The device of  claim 17 , wherein:
 the performance parameters are programmed into the performance parameter table in response to a program signal. 
 
     
     
       19. The device of  claim 16 , further including:
 a buffer circuit coupled to receive data externally to the device at a data terminal and provide the data to the performance parameter table, wherein the performance parameter table addresses a location in response to the value of the data. 
 
     
     
       20. The device of  claim 16 , wherein:
 the device is a semiconductor device.