Semiconductor devices

Abstract

A semiconductor device with impedance calibration includes a first channel circuit of a first channel and a second channel circuit of a second channel. The first channel circuit is configured to drive a first node in response to a flag signal, generate a start signal from a signal of the first node to execute a first calibration operation in response to a mask signal, and generate and output an end signal after termination of the first calibration operation. The second channel circuit is configured to generate a transmission start signal from the end signal to execute a second calibration operation.

What is claimed is: 
     
       1. A semiconductor device comprising:
 a first channel circuit of a first channel configured to drive a first node in response to a flag signal, configured to generate a start signal from a signal of the first node to execute a first calibration operation in response to a mask signal, and configured to generate and output an end signal after termination of the first calibration operation; and 
 a second channel circuit of a second channel configured to generate a transmission start signal from the end signal to execute a second calibration operation, 
 wherein the flag signal is set to a first level if a calibration command is inputted to a second node included in the second channel circuit and is set to a second level if the calibration command is inputted to the first node included in the first channel circuit. 
 
     
     
       2. The semiconductor device of  claim 1 , wherein the first channel circuit receives the calibration command inputted to the second node to drive the first node if the flag signal is set to the first level. 
     
     
       3. The semiconductor device of  claim 1 , wherein the first calibration operation is an operation that calibrates an impedance of an on-die termination (ODT) circuit included in the first channel circuit. 
     
     
       4. The semiconductor device of  claim 1 , wherein the second channel circuit includes an output driver that drives a first pad in response to a signal of the second node to which the calibration command is inputted. 
     
     
       5. The semiconductor device of  claim 4 , wherein the first channel circuit includes an input driver that drives the first node in response to a signal of a second pad connected to the first pad. 
     
     
       6. The semiconductor device of  claim 5 , wherein the first channel circuit further includes a start signal generation circuit that generates the start signal in response to the mask signal and a signal of the first node. 
     
     
       7. The semiconductor device of  claim 1 , wherein the first channel circuit includes an output driver that receives the end signal to drive a first pad in response to the mask signal. 
     
     
       8. The semiconductor device of  claim 7 , wherein the second channel circuit includes an input driver that drives the transmission start signal in response to a signal of a second pad connected to the first pad. 
     
     
       9. The semiconductor device of  claim 1 , wherein the first channel circuit includes a mask signal generation circuit that generates the mask signal driven in response to the flag signal and the end signal after termination of a power-up period. 
     
     
       10. A semiconductor device comprising:
 a first command input/output (I/O) circuit configured to be included in a first channel circuit of a first channel and configured to receive a signal of a first pad to drive a first node in response to a first flag signal or to receive a signal of the first node to drive the first pad in response to the first flag signal; 
 a first start signal generation circuit configured to be included in the first channel circuit and configured to buffer a signal of the first node to generate a first start signal for a first calibration operation in response to a first mask signal; and 
 a first end pulse input/output (I/O) circuit configured to be included in the first channel circuit and configured to drive a second pad in response to a first end signal generated after termination of the first calibration operation or to drive a first transmission start signal for the first calibration operation in response to a signal of the second pad. 
 
     
     
       11. The semiconductor device of  claim 10 , wherein the first flag signal is set to a first level if a calibration command is inputted to a second node included in a second channel circuit and is set to a second level if the calibration command is inputted to the first node included in the first channel circuit. 
     
     
       12. The semiconductor device of  claim 11 , wherein the first command I/O circuit includes:
 an input driver configured to drive the first node in response to a signal of the first pad if the first flag signal has the first level; and 
 an output driver configured to drive the first pad in response to a signal of the first node if the first flag signal has the second level. 
 
     
     
       13. The semiconductor device of  claim 10 , wherein the first end pulse I/O circuit includes:
 an output driver configured to receive the first end signal to drive the second pad in response to the first mask signal; and 
 an input driver configured to receive a signal of the second pad to drive the first transmission start signal in response to a second mask signal. 
 
     
     
       14. The semiconductor device of  claim 10 , further comprising a first mask signal generation circuit configured to be included in the first channel circuit and configured to generate the first mask signal that is driven in response to the first flag signal, the first end signal and the first transmission start signal after termination of a power-up period. 
     
     
       15. The semiconductor device of  claim 14 , wherein the first mask signal generation circuit includes:
 a first drive circuit configured to drive an internal node to a first level in response to a power-up signal and the first flag signal; and 
 a second drive circuit configured to drive the internal node to a second level in response to the power-up signal and the first flag signal. 
 
     
     
       16. The semiconductor device of  claim 15 , wherein the first mask signal generation circuit further includes a third drive circuit configured to drive the internal node in response to the first transmission start signal and the first end signal. 
     
     
       17. The semiconductor device of  claim 10 , further comprising a second command I/O circuit configured to be included in a second channel circuit of a second channel and configured to receive a signal of a third pad to drive a second node in response to a second flag signal or to receive a signal of the second node to drive the third pad in response to the second flag signal. 
     
     
       18. The semiconductor device of  claim 10 , further comprising a second start signal generation circuit configured to be included in a second channel circuit of a second channel and configured to buffer a signal of a second node to generate a second start signal for a second calibration operation in response to a second mask signal. 
     
     
       19. The semiconductor device of  claim 10 , further comprising a second end pulse I/O circuit configured to be included in a second channel circuit of a second channel and configured to drive a third pad in response to a second end signal generated after termination of a second calibration operation or to drive a second transmission start signal for the second calibration operation in response to a signal of the third pad. 
     
     
       20. The semiconductor device of  claim 14 , further comprising a second mask signal generation circuit configured to be included in a second channel circuit of a second channel and configured to generate a second mask signal that is driven in response to the second flag signal, a second end signal and a second transmission start signal after termination of a power-up period.