Selectable memory access time

Abstract

The present disclosure relates to selectable memory access time. An apparatus includes a memory controller. The memory controller is configured to select a memory access time interval duration parameter based, at least in part, on a memory address identifier, in response to receiving a memory access request; to adjust the selected memory access time interval duration parameter based, at least in part, on a current operating temperature; and perform a requested memory access operation on a memory array, a duration of the memory access operation related to the adjusted memory access time interval duration parameter.

What is claimed is: 
     
       1. An apparatus comprising:
 a memory controller configured to allow a target node in a memory array to transition from an initial state to a dwell state and back to the initial state by selecting a memory access time interval duration parameter based, at least in part, on a memory address identifier, in response to receiving a memory access request; to adjust the selected memory access time interval duration parameter based, at least in part, on a current operating temperature; and 
 
       perform a requested memory access operation on the memory array, a duration of the memory access operation related to the adjusted memory access time interval duration parameter. 
     
     
       2. The apparatus of  claim 1 , wherein the memory controller is further configured to determine the memory access time interval duration parameter; associate the memory access time interval duration parameter with the memory address identifier; and store the memory access time interval duration parameter and the associated memory address identifier in a parameter store. 
     
     
       3. The apparatus of  claim 2 , wherein the memory controller is further configured to determine a temperature adjustment parameter, associate the temperature adjustment parameter with the memory address identifier and store the temperature adjustment parameter to the parameter store. 
     
     
       4. The apparatus of  claim 1 , wherein the memory controller is further configured to determine the current operating temperature and to select a temperature adjustment parameter based, at least in part, on the memory address identifier, the adjusted memory access time interval duration parameter related to the temperature adjustment parameter. 
     
     
       5. The apparatus of  claim 1 , wherein a memory access time interval comprises a precharge time interval configured to transition the target node from an initial state to a target state, a duration of the precharge time interval related to a coupling structure of the memory array. 
     
     
       6. The apparatus of  claim 2 , wherein the memory access time interval parameter is predetermined based, at least in part, on a coupling structure geometry of the memory array. 
     
     
       7. The apparatus of  claim 2 , wherein the memory access time interval parameter is determined iteratively, based, at least in part, on a number of trials of memory access operations. 
     
     
       8. A method comprising:
 allowing, by a memory controller, a target node in a memory array to transition from an initial state to a dwell state and back to the initial state by selecting, by the memory controller, a memory access time interval duration parameter based, at least in part, on a memory address identifier, in response to receiving a memory access request; 
 adjusting, by the memory controller, the selected memory access time interval duration parameter based, at least in part, on a current operating temperature; and 
 performing, by the memory controller, a requested memory access operation on the memory array, a duration of the memory access operation related to the adjusted memory access time interval duration parameter. 
 
     
     
       9. The method of  claim 8 , further comprising:
 determining, by the memory controller, the memory access time interval duration parameter; 
 associating, by the memory controller, the memory access time interval duration parameter with the memory address identifier; and 
 storing, by the memory controller, the memory access time interval duration parameter and the associated memory address identifier in a parameter store. 
 
     
     
       10. The method of  claim 8 , further comprising:
 determining, by the memory controller, the current operating temperature; and 
 selecting, by the memory controller, a temperature adjustment parameter based, at least in part, on the memory address identifier, the adjusted memory access time interval duration parameter related to the temperature adjustment parameter. 
 
     
     
       11. The method of  claim 9 , further comprising:
 determining, by the memory controller, a temperature adjustment parameter; 
 associating, by the memory controller, the temperature adjustment parameter with the memory address identifier; and 
 storing, by the memory controller, the temperature adjustment parameter to the parameter store. 
 
     
     
       12. The method of  claim 11 , wherein the temperature adjustment parameter is related to a change in resistance with temperature of a coupling structure associated with the memory address identifier. 
     
     
       13. The method of  claim 8 , wherein a memory access time interval comprises a precharge time interval configured to transition the target node from an initial state to a target state, a duration of the precharge time interval related to a coupling structure of the memory array. 
     
     
       14. The method of  claim 8 , wherein the memory array comprises a three dimensional memory architecture. 
     
     
       15. The method of  claim 9 , wherein the memory access time interval parameter is predetermined based, at least in part, on a coupling structure geometry of the memory array. 
     
     
       16. The method of  claim 9 , wherein the memory access time interval parameter is determined iteratively, based, at least in part, on a number of trials of memory access operations. 
     
     
       17. A system comprising:
 a processor; 
 a chipset configured to couple the processor to a peripheral device; 
 a memory array comprising a plurality of memory cells; and 
 a memory controller configured to allow a memory cell in the memory array to transition from an initial state to a dwell state and back to the initial state by selecting a memory access time interval duration parameter based, at least in part, on a memory address identifier, in response to receiving a memory access request; to adjust the selected memory access time interval duration parameter based, at least in part, on a current operating temperature; and 
 
       perform a requested memory access operation on the memory array, a duration of the memory access operation related to the adjusted memory access time interval duration parameter. 
     
     
       18. The system of  claim 17 , wherein the memory controller is further configured to determine the memory access time interval duration parameter; associate the memory access time interval duration parameter with the memory address identifier; and store the memory access time interval duration parameter and the associated memory address identifier in a parameter store. 
     
     
       19. The system of  claim 17 , wherein the memory controller is further configured to determine a temperature adjustment parameter, associate the temperature adjustment parameter with the memory address identifier and store the temperature adjustment parameter to the parameter store. 
     
     
       20. The system of  claim 17 , wherein the memory controller is further configured to determine the current operating temperature and to select a temperature adjustment parameter based, at least in part, on the memory address identifier, the adjusted memory access time interval duration parameter related to the temperature adjustment parameter. 
     
     
       21. The system of  claim 19 , wherein the temperature adjustment parameter is related to a change in resistance with temperature of a coupling structure associated with the memory address identifier. 
     
     
       22. The system of  claim 17 , wherein a memory access time interval comprises a precharge time interval configured to transition a memory cell from an initial state to a target state, a duration of the precharge time interval related to a coupling structure of the memory array. 
     
     
       23. The system of  claim 17 , wherein the memory array comprises a three dimensional memory architecture. 
     
     
       24. The system of  claim 18 , wherein the memory access time interval parameter is predetermined based, at least in part, on a coupling structure geometry of the memory array. 
     
     
       25. The system of  claim 18 , wherein the memory access time interval parameter is determined iteratively, based, at least in part, on a number of trials of memory access operations.