Systems and methods for detecting and preventing optical attacks

Abstract

The present disclosure outlines various systems and methods for detecting an optical fault injection within an electronic device and/or preventing the optical fault injection from introducing an exploitable abnormality within the electronic device. These various systems and methods can include systems and methods that can detect or prevent laser injection attacks, which can include one or more small footprint complementary metal oxide silicon (CMOS) light detection circuits, or structures that can shield one or more transistors from a bottom side laser injection attack.

What is claimed is: 
     
       1. An integrated circuit formed onto a semiconductor substrate for detecting a laser injection attack, the integrated circuit comprising:
 a first diffusion region, within the semiconductor substrate, that forms a first region of a first transistor; and 
 a second diffusion region, within the semiconductor substrate, that forms a second region of a second transistor, 
 wherein the first transistor and the second transistor are implemented as part of a latching circuit, the latching circuit being at a first logical level and changing to a second logical level, different from the first logical level, in response to a first charge being accepted by or donated to the semiconductor substrate by the first diffusion region or a second charge being donated to or accepted by the semiconductor substrate during the laser injection attack. 
 
     
     
       2. The integrated circuit of  claim 1 , wherein the first diffusion region comprises a p-type diffusion layer, and
 wherein the second diffusion region comprises an n-type diffusion layer. 
 
     
     
       3. The integrated circuit of  claim 1 , wherein the first transistor and the second transistor are a p-type transistor and an n-type transistor, respectively, and
 wherein the first diffusion region and the second diffusion region comprise:
 a drain region of the p-type transistor and a drain region of the n-type transistor, respectively. 
 
 
     
     
       4. The integrated circuit of  claim 1 , wherein the size of the first diffusion region is less than the size of the second diffusion region, and
 wherein the first charge accepted or donated by the first diffusion region is less than the second charge donated or accepted by the second diffusion region during the laser injection attack. 
 
     
     
       5. The integrated circuit of  claim 1 , wherein the size of the first diffusion region is greater than the size of the second diffusion region, and
 wherein the first charge accepted or donated by the first diffusion region is greater than the second charge donated or accepted by the second diffusion region during the laser injection attack. 
 
     
     
       6. The integrated circuit of  claim 1 , wherein the first diffusion region is configured to be charged to a logical low and to change to a logical high and the second diffusion region is configured to be charged to a logical high and to change to a logical low during the laser injection attack. 
     
     
       7. The integrated circuit of  claim 1 , wherein the first diffusion region is configured to be charged to a logical high and to change to a logical low and the second diffusion region is configured to be charged to a logical low and to change to a logical high during the laser injection attack. 
     
     
       8. The integrated circuit of  claim 1 , wherein the latching circuit is a set-reset (S-R) latch, the S-R latch comprising:
 a first logical NAND gate cross-coupled with a second logical NAND gate, 
 wherein the first logical NAND gate includes the first transistor, and 
 wherein the second logical NAND gate includes the second transistor. 
 
     
     
       9. An integrated circuit formed onto a semiconductor substrate for detecting a laser injection attack, the integrated circuit comprising:
 a first transistor formed within a first diffusion region of the semiconductor substrate; and 
 a second transistor formed within a second diffusion region of the semiconductor substrate, 
 wherein the first transistor and the second transistor are implemented as part of a latching circuit, the latching circuit being at a first logical level and changing to a second logical level, different from the first logical level, in response to a first charge being accepted by or donated to the semiconductor substrate by the first diffusion region or a second charge being donated to or accepted by the semiconductor substrate during the laser injection attack. 
 
     
     
       10. The integrated circuit of  claim 9 , wherein the first diffusion region comprises a p-type diffusion layer, and wherein the second diffusion region comprises an n-type diffusion layer. 
     
     
       11. The integrated circuit of  claim 9 , wherein the first transistor and the second transistor are a p-type transistor and an n-type transistor, respectively, and
 wherein the first diffusion region and the second diffusion region comprise:
 a drain region of the p-type transistor and a drain region of the n-type transistor, respectively. 
 
 
     
     
       12. The integrated circuit of  claim 9 , wherein the size of the first diffusion region is less than the size of the second diffusion region, and
 wherein the first charge accepted or donated by the first diffusion region is less than the second charge donated or accepted by the second diffusion region during the laser injection attack. 
 
     
     
       13. The integrated circuit of  claim 9 , wherein the size of the first diffusion region is greater than the size of the second diffusion region, and
 wherein the first charge accepted or donated by the first diffusion region is greater than the second charge donated or accepted by the second diffusion region during the laser injection attack. 
 
     
     
       14. The integrated circuit of  claim 9 , wherein the first diffusion region is configured to be charged to a logical low and to change to a logical high and the second diffusion region is configured to be charged to a logical high and to change to a logical low during the laser injection attack. 
     
     
       15. The integrated circuit of  claim 9 , wherein the first diffusion region is configured to be charged to a logical high and to change to a logical low and the second diffusion region is configured to be charged to a logical low and to change to a logical high during the laser injection attack. 
     
     
       16. The integrated circuit of  claim 9 , wherein the latching circuit is a set-reset (S-R) latch, the S-R latch comprising:
 a first logical NAND gate cross-coupled with a second logical NAND gate, 
 wherein the first logical NAND gate includes the first transistor, and 
 wherein the second logical NAND gate includes the second transistor. 
 
     
     
       17. A latching circuit formed onto a semiconductor substrate for detecting a laser injection attack, the latching circuit comprising:
 a first transistor formed within a first diffusion region of the semiconductor substrate; and 
 a second transistor formed within a second diffusion region of the semiconductor substrate, 
 wherein the latching circuit is configured to be at a first logical level and to change to a second logical level, different from the first logical level, in response to a first charge being accepted by or donated to the semiconductor substrate by the first diffusion region or a second charge being donated to or accepted by the semiconductor substrate during the laser injection attack. 
 
     
     
       18. The latching circuit of  claim 17 , wherein the latching circuit is a set-reset (S-R) latch, the S-R latch comprising:
 a first logical NAND gate cross-coupled with a second logical NAND gate, 
 wherein the first logical NAND gate includes the first transistor, and 
 wherein the second logical NAND gate includes the second transistor. 
 
     
     
       19. The latching circuit of  claim 18 , wherein the first diffusion region is coupled to a first input of the latching circuit, and
 wherein the second diffusion region is coupled to a second input of the latching circuit. 
 
     
     
       20. The latching circuit of  claim 17 , wherein the first transistor and the second transistor are a p-type transistor and an n-type transistor, respectively, and
 wherein the first diffusion region and the second diffusion region comprise:
 a drain region of the p-type transistor and a drain region of the n-type transistor, respectively.