Semiconductor device having air gap and method for manufacturing the same, memory cell having the same and electronic device having the same

Abstract

A semiconductor device including a substrate including an active region and a device isolation region that isolates the active region, and a buried bit line and a buried gate electrode formed in the substrate. The device isolation region includes a first device isolation region extending in a first direction and a second device isolation region extending in a second direction crossing with the first direction and having an formed air gap.

What is claimed is: 
     
       1. A semiconductor device comprising:
 a semiconductor substrate comprising an active region, and a device isolation region that isolates the active region; and 
 a buried bit line and a buried gate electrode formed in the semiconductor substrate, 
 wherein the device isolation region comprises: 
 a first device isolation region extending in a first direction; and 
 a second device isolation region extending in a second direction crossing with the first direction, and having an air gap, 
 wherein the buried bit line is formed in a bit line trench extending in a third direction crossing with the first and second directions. 
 
     
     
       2. The semiconductor device according to  claim 1 ,
 wherein the active region extends in the first direction and the second direction, 
 wherein the first device isolation region is positioned between neighboring active regions in the second direction, and 
 wherein the second device isolation region is positioned between neighboring active regions in the first direction. 
 
     
     
       3. The semiconductor device according to  claim 1 ,
 further comprising a first isolation trench extending in the first direction, 
 wherein the first device isolation region is formed in the first isolation trench. 
 
     
     
       4. The semiconductor device according to  claim 1 ,
 further comprising a second isolation trench extending in the second direction, 
 wherein the second device isolation region is formed in the second isolation trench. 
 
     
     
       5. The semiconductor device according to  claim 4 , wherein the second isolation trench comprises:
 an upper isolation trench; and 
 a lower isolation trench that has a bulb shape and is wider than the upper isolation trench, 
 wherein the air gap is formed in the lower isolation trench. 
 
     
     
       6. The semiconductor device according to  claim 1 ,
 further comprising a gate trench comprising a bottom surface, a first side surface and a second side surface opposite to the first side surface, 
 wherein the buried gate electrode is formed in the gate trench. 
 
     
     
       7. The semiconductor device according to  claim 6 , wherein the gate trench comprises:
 a first trench extending in the second direction; and 
 second and third trenches stemming from the first trench and extending in the first direction. 
 
     
     
       8. The semiconductor device according to  claim 7 , wherein the buried gate electrode comprises:
 a first electrode buried in the first trench of the gate trench; 
 a second electrode buried in the second trench of the gate trench; and 
 a third electrode buried in the third trench of the gate trench. 
 
     
     
       9. The semiconductor device according to  claim 1 ,
 further comprising a body trench under the buried bit line and a punch-through prevention layer formed in the body trench, 
 wherein the punch-through prevention layer is positioned in the active region. 
 
     
     
       10. The semiconductor device according to  claim 1 ,
 wherein the active region comprises a body and a pillar vertically extending over the body, and 
 wherein the pillar comprises: 
 a first junction region electrically coupled to the bit line; 
 a second junction region vertically positioned relative to the first junction region; and 
 a channel positioned between the first and second junction regions, and overlapping with the buried gate electrode. 
 
     
     
       11. The semiconductor device according to  claim 10 , further comprising a memory element electrically coupled to the second junction region. 
     
     
       12. A semiconductor device comprising:
 a semiconductor substrate comprising an active region, and a device isolation region that isolates the active region; and 
 a buried bit line and a buried gate electrode formed in the substrate, 
 wherein the device isolation region comprises: 
 a first device isolation region extending in a first direction and having a first air gap; and 
 a second device isolation region extending in a second direction crossing with the first direction, and having a second air gap, and 
 wherein the active region is defined by the first and second device isolation regions, 
 wherein the buried bit line is formed in a bit line trench extending in a third direction crossing with the first and second directions. 
 
     
     
       13. The semiconductor device according to  claim 12 ,
 wherein the active region extends in the first direction and a the second direction, 
 wherein the first device isolation region is positioned between neighboring active regions in the second direction, and 
 wherein the second device isolation region is positioned between neighboring active regions in the first direction. 
 
     
     
       14. The semiconductor device according to  claim 12 ,
 wherein the semiconductor substrate comprises a line type first isolation trench extending in the first direction, and 
 wherein the first device isolation region is formed in the first isolation trench. 
 
     
     
       15. The semiconductor device according to  claim 12 ,
 wherein the semiconductor substrate further comprises a second isolation trench extending in the second direction, and 
 wherein the second device isolation region is formed in the second isolation trench. 
 
     
     
       16. The semiconductor device according to  claim 15 ,
 wherein the second isolation trench comprises: 
 an upper isolation trench; and 
 a lower isolation trench that has a bulb shape and is wider than the upper isolation trench, and 
 wherein the first air gap is formed in the lower isolation trench. 
 
     
     
       17. The semiconductor device according to  claim 12 , further comprising a body trench under the buried bit line and a punch-through prevention layer formed in the body trench. 
     
     
       18. The semiconductor device according to  claim 12 , wherein the semiconductor substrate further comprises a pillar comprising:
 a first junction region electrically coupled to the buried bit line; 
 a second junction region vertically positioned relative to the first junction region; and 
 a vertical channel positioned between the first and second junction regions, and overlapping with the gate electrode.