Semiconductor memory device

Abstract

A semiconductor memory device includes a memory cell, a bit line electrically connected to a first end of the memory cell, a source line electrically connected to a second end of the memory cell, a sense amplifier electrically connected to the bit line, and a controller configured to perform a read operation including first and second read operations on the memory cell. During the first read operation, a pre-charge voltage is applied to the bit line and a source line voltage lower than the pre-charge voltage is applied to the source line, and during the second read operation, a first voltage that is greater than the source line voltage and less than the pre-charge voltage is applied to the bit line.

What is claimed is: 
     
       1. A semiconductor memory device comprising:
 a memory cell; 
 a bit line electrically connected to a first end of the memory cell; 
 a source line electrically connected to a second end of the memory cell; 
 a sense amplifier electrically connected to the bit line; and 
 a controller configured to perform a read operation including first and second read operations on the memory cell, 
 wherein, during the first read operation, a pre-charge voltage is applied to the bit line and a source line voltage lower than the pre-charge voltage is applied to the source line, and during the second read operation, a first voltage that is greater than the source line voltage and less than the pre-charge voltage is applied to the bit line. 
 
     
     
       2. The device according to  claim 1 ,
 wherein the memory cell stores two or more bits of data and the first and second read operations are performed to distinguish among at least four threshold voltage levels of the memory cell. 
 
     
     
       3. The device according to  claim 2 ,
 wherein the memory cell is maintained off during the first read operation. 
 
     
     
       4. The device according to  claim 1 ,
 wherein the memory cell stores two or more bits of data and the read operation further includes third and fourth read operations, and 
 wherein the first, second, third, and fourth read operations are performed to distinguish among at least four threshold voltage levels of the memory cell. 
 
     
     
       5. The device according to  claim 4 ,
 wherein the memory cell is turned on during the first read operation. 
 
     
     
       6. The device according to  claim 1 ,
 wherein the read operation is performed as a verification operation after a write operation. 
 
     
     
       7. The device according to  claim 1 , further comprising:
 a voltage generation circuit configured to generate the first voltage. 
 
     
     
       8. The device according to  claim 7 ,
 wherein during the second read operation, the sense amplifier initially applies the source line voltage to the bit line and then applies the first voltage to the bit line. 
 
     
     
       9. The device according to  claim 1 ,
 wherein the sense amplifier includes a current limiting circuit configured to set the first voltage by limiting a current flowing to the bit line. 
 
     
     
       10. A method of performing a read operation including first and second read operations in a semiconductor memory device having a memory cell, a bit line electrically connected to a first end of the memory cell, a source line electrically connected to a second end of the memory cell, and a sense amplifier electrically connected to the bit line, said method comprising:
 during the first read operation, applying a pre-charge voltage to the bit line and a source line voltage lower than the pre-charge voltage to the source line; and 
 during the second read operation, applying a first voltage that is greater than the source line voltage and less than the pre-charge voltage to the bit line. 
 
     
     
       11. The method according to  claim 10 ,
 wherein the memory cell stores two or more bits of data and the first and second read operations are performed to distinguish among at least four threshold voltage levels of the memory cell. 
 
     
     
       12. The method according to  claim 11 ,
 wherein the memory cell is maintained off during the first read operation. 
 
     
     
       13. The method according to  claim 10 ,
 wherein the memory cell stores two or more bits of data and the read operation further includes third and fourth read operations, and 
 wherein the first, second, third, and fourth read operations are performed to distinguish among at least four threshold voltage levels of the memory cell. 
 
     
     
       14. The method according to  claim 13 ,
 wherein the memory cell is turned on during the first read operation. 
 
     
     
       15. The method according to  claim 10 ,
 wherein the read operation is performed as a verification operation after a write operation. 
 
     
     
       16. The method according to  claim 10 ,
 wherein the semiconductor memory device further comprising a voltage generation circuit configured to generate the first voltage. 
 
     
     
       17. The method according to  claim 16 ,
 wherein during the second read operation, the sense amplifier initially applies the source line voltage to the bit line and then applies the first voltage to the bit line. 
 
     
     
       18. The method according to  claim 10 ,
 wherein the sense amplifier includes a current limiting circuit configured to set the first voltage by limiting a current flowing to the bit line. 
 
     
     
       19. A semiconductor memory device comprising:
 first and second memory cells, each configured to store two or more bits; 
 a first bit line electrically connected to a first end of the first memory cell; 
 a second bit line electrically connected to a first end of the second memory cell; 
 a source line electrically connected to second ends of the first and second memory cells; 
 a sense amplifier electrically connected to the first and second bit lines; and 
 a controller configured to perform a read operation including first, second, third, and fourth read operations on the memory cell, to distinguish among at least four threshold voltage levels of the first and second memory cells, wherein 
 during the first read operation, a pre-charge voltage is applied to the first and second bit lines and a source line voltage lower than the pre-charge voltage is applied to the source line, 
 during the second read operation, the pre-charge voltage is applied to the first bit line and a first voltage that is greater than the source line voltage and less than the pre-charge voltage is applied to the second bit line, 
 during the third read operation, the pre-charge voltage is applied to the first bit line, and 
 during the fourth read operation, the first voltage is applied to the first bit line. 
 
     
     
       20. The device according to  claim 19 ,
 wherein the first memory cell is maintained off during the first read operation and turned on during the second and third read operations, and the second memory cell is turned on during the first read operation.