Set-partitioned coded modulation with multiple encodings

Abstract

An outer encoder encodes input data signal to generate a first encoded signal. An inner encoder encodes a subset of the input data to generate a second encoded signal, wherein the inner encoder has a different forward error correction (FEC) than the outer encoder. A symbol mapper processes the first encoded signal and the second encoded signal to generate a sequence of discrete-valued modulation symbols.

What is claimed is: 
     
       1. An apparatus, comprising:
 an outer encoder to encode a first subset of input data to generate a first encoded signal; 
 an inner encoder to encode a second subset of the input data to generate a second encoded signal, wherein the inner encoder has a different forward error correction (FEC) than the outer encoder and wherein the second subset and the first subset are dynamically selected of adjustable bit sizes, based on channel conditions; and 
 a symbol mapper, coupled to the outer encoder and the inner encoder, to process the first encoded signal and the second encoded signal to generate a sequence of discrete-valued modulation symbols. 
 
     
     
       2. The apparatus of  claim 1 , wherein the outer encoder includes:
 an FEC encoder that generates an FEC encoded signal based on the first subset of input data; and 
 an interleaver, coupled to the FEC encoder, to generate the first encoded signal by interleaving the FEC encoded signal. 
 
     
     
       3. The apparatus of  claim 2 , wherein:
 the interleaver includes a convolutional interleaver. 
 
     
     
       4. The apparatus of  claim 1 , wherein the outer encoder includes:
 an FEC encoder that generates an FEC encoded signal based on the first subset of input data; 
 an interleaver, coupled to the FEC encoder, to generate an interleaved encoded signal by interleaving the FEC encoded signal; and 
 a symbol converter, coupled to the interleaver, to generate the first encoded signal from the interleaved encoded signal. 
 
     
     
       5. The apparatus of  claim 1 , further comprising:
 a modulator, coupled to the symbol mapper, to process the sequence of discrete-valued modulation symbols to generate a continuous-time signal for transmission via a communication channel. 
 
     
     
       6. The apparatus of  claim 5 , wherein:
 the continuous-time signal is a set partition coded modulation (SPCM) signal. 
 
     
     
       7. The apparatus of  claim 1 , wherein:
 the second subset of the input data is a plurality of least significant bits of the input data. 
 
     
     
       8. The apparatus of  claim 1 , wherein:
 the symbol mapper processes the first encoded signal as a plurality of most significant bits and the second encoded signal as a plurality of least significant bits to generate the sequence of discrete-valued modulation symbols. 
 
     
     
       9. The apparatus of  claim 1 , wherein:
 the outer encoder includes a Reed-Solomon (RS) encoder. 
 
     
     
       10. The apparatus of  claim 1 , wherein:
 the inner encoder includes a low density parity check (LDPC) encoder. 
 
     
     
       11. A method, comprising:
 outer encoding a first subset of input data in a cable communication system to generate a first encoded signal; 
 inner encoding a second subset of the input data to generate a second encoded signal, wherein the inner encoding has a different forward error correction (FEC) than the outer encoding and wherein the second subset and the first subset are dynamically selected of adjustable bit sizes, based on current conditions; and 
 symbol mapping the first encoded signal and the second encoded signal to generate a sequence of discrete-valued modulation symbols. 
 
     
     
       12. The method of  claim 11 , wherein the outer encoding includes:
 generating an FEC encoded signal based on the first subset of the input data; and 
 generating the first encoded signal by interleaving the FEC encoded signal. 
 
     
     
       13. The method of  claim 12 , wherein:
 interleaving includes convolutional interleaving. 
 
     
     
       14. The method of  claim 11 , wherein the outer encoding includes:
 generating an FEC encoded signal; 
 generating an interleaved encoded signal by interleaving the FEC encoded signal; and 
 generating the first encoded signal from the interleaved encoded signal. 
 
     
     
       15. The method of  claim 11 , further comprising:
 processing the sequence of discrete-valued modulation symbols to generate a continuous-time signal for transmission via a cable communication channel; 
 wherein the continuous-time signal is a set partition coded modulation (SPCM) signal. 
 
     
     
       16. The method of  claim 11 , wherein:
 the second subset of the input data is a plurality of least significant bits of the input data. 
 
     
     
       17. The method of  claim 11 , wherein:
 symbol mapping includes processing the first encoded signal as a plurality of most significant bits and the second encoded signal as a plurality of least significant bits to generate the sequence of discrete-valued modulation symbols. 
 
     
     
       18. The method of  claim 11 , wherein:
 the outer encoding includes a Reed-Solomon (RS) encoding. 
 
     
     
       19. The method of  claim 11 , wherein:
 the inner encoding includes a low density parity check (LDPC) encoding. 
 
     
     
       20. An apparatus, comprising:
 an outer encoder to encode a first subset of input data in blocks of a first bit length to generate a first encoded signal; 
 an inner encoder to encode a second subset of the input data that includes most significant bits of the input data in blocks of a second bit length to generate a second encoded signal, wherein the first bit length and the second bit length are dynamically selected, based on current conditions; and 
 a symbol mapper, coupled to the outer encoder and the inner encoder, to process the first encoded signal and the second encoded signal to generate a sequence of discrete-valued modulation symbols.