Structure and method for 3D IC package

Abstract

A chip package may include: a first die; a second die; an underfill disposed between and in physical contact with the first die and the second die; and one or more conductive elements encapsulated in the underfill and coupling the first die and the second die to each other.

What is claimed is: 
     
       1. A chip package comprising:
 a first die comprising a semiconductor substrate; 
 a second die; 
 an underfill disposed between and in physical contact with the semiconductor substrate of the first die and the second die; 
 one or more conductive elements encapsulated in the underfill and coupling the first die and the second die to each other; and 
 one or more interconnection layers disposed at a side of the semiconductor substrate facing away from the underfill, the one or more interconnection layers electrically coupled to the one or more conductive elements encapsulated in the underfill by one or more through-vias extending through the semiconductor substrate. 
 
     
     
       2. The chip package of  claim 1 , further comprising:
 a first molding compound encapsulating the first die; and 
 a second molding compound encapsulating the second die and the underfill, wherein peripheral regions of the first molding compound and the second molding compound physically contact each other. 
 
     
     
       3. The chip package of  claim 1 , wherein a width of the second die and a width of the underfill are greater than a width of the first die. 
     
     
       4. The chip package of  claim 1 , further comprising:
 a redistribution layer (RDL) coupled to the first die, the RDL disposed at a side of the first die facing away from the underfill; and 
 an interconnect structure disposed at a side of the RDL facing away from the first die, the interconnect structure comprising a plurality of connectors for three-dimensional fan-out coupled to the RDL. 
 
     
     
       5. The chip package of  claim 1 , wherein the one or more conductive elements encapsulated in the underfill comprises an under-bump metallization element, a solder element, or combinations thereof. 
     
     
       6. The chip package of  claim 1 , wherein the first die and the second die comprise a plurality of layers of stacked chip logic. 
     
     
       7. The chip package of  claim 1 , wherein the first die is a system on chip (SoC) die. 
     
     
       8. A chip package comprising:
 a first die; 
 a first molding compound encapsulating the first die; 
 a second die coupled to the first die via conductive elements; 
 an underfill between the first die and the second die encapsulating the conductive elements; 
 a second molding compound encapsulating the second die and the underfill on the first die; 
 a redistribution layer (RDL) on one side of the first die opposite to the underfill; and 
 a plurality of connectors providing a three-dimensional fan-out structure on one side of the RDL opposite to the first die. 
 
     
     
       9. The chip package of  claim 8 , wherein the second die over the first die forms an overhang structure, and wherein the first molding compound encapsulating the first die, the underfill between the first die and the second die, and the second molding compound encapsulating the second die provide mechanical support to the overhang structure. 
     
     
       10. The chip package of  claim 8 , wherein the second molding compound is in contact with the first molding compound. 
     
     
       11. The chip package of  claim 8 , wherein the first die is coupled to first conductive elements and the second die is coupled to second conductive elements, and wherein the first conductive elements are coupled to the second conductive elements inside the underfill. 
     
     
       12. The chip package of  claim 11 , wherein the connectors are coupled through the RDL to a combination of through vias and pads in the first die, and wherein the through vias and pads are coupled to the first conductive elements. 
     
     
       13. The chip package of  claim 8 , wherein the first die and the second die comprise a plurality of layers of stacked chip logic. 
     
     
       14. A chip package comprising:
 a first chip encapsulated in a first molding compound; and 
 a second chip wider than the first chip and coupled to the first chip via conductive elements, 
 wherein the conductive elements are encapsulated in an underfill between the first chip and the second chip without an interposer; 
 wherein the second chip and the underfill are encapsulated in a second molding compound in contact with the first molding compound; and 
 wherein the second chip comprises:
 one or more layers, and 
 a semiconductor substrate attached to the one or more layers. 
 
 
     
     
       15. The chip package of  claim 14 , wherein the first chip is a system on chip (SoC) die comprising:
 stacked chip logic with through vias and pads across the stacked chips logic; and 
 a semiconductor substrate attached to the stacked chip logic and including second through vias coupled to the through vias and pads. 
 
     
     
       16. The chip package of  claim 14 , wherein the conductive elements encapsulated in the underfill comprise:
 first conductive elements added to the first chip; 
 second conductive elements added to the second chip; and 
 joints that couple between the first conductive elements and the second conductive elements. 
 
     
     
       17. The chip package of  claim 14 , further comprising:
 a redistribution layer (RDL) coupled to the first chip, wherein the first chip is positioned between the underfill and the RDL; and 
 an interconnect structure comprising a plurality of connectors for three-dimensional fan-out coupled to the RDL, wherein the RDL is positioned between the first chip and the interconnect structure. 
 
     
     
       18. The chip package of  claim 17 , wherein the RDL comprises a conductive layer coupled to the first chip and further a polymer layer coupled to the conductive layer and the interconnect structure, and wherein the interconnect structure is a ball grid array (BGA) comprising a plurality of conductive spheres coupled to the conductive layer. 
     
     
       19. The chip package of  claim 1 , wherein the first die is coupled to first conductive elements and the second die is coupled to second conductive elements, and wherein the first conductive elements are coupled to the second conductive elements inside the underfill. 
     
     
       20. The chip package of  claim 14 , wherein the first chip and the second chip comprise a plurality of layers of stacked chip logic.