Vertical structure non-volatile memory device having insulating regions that are formed as air gaps

Abstract

A vertical structure non-volatile memory device includes semiconductor regions that vertically extend on a substrate, a plurality of memory cell strings that vertically extend on the substrate along sidewalls of the semiconductor regions and include a plurality of memory cells and at least one or more first selection transistors, which are disposed on sides of the memory cells and are adjacent to one another. A plurality of wordlines is connected to the memory cells of the memory cell strings. A first selection line is connected to the selection transistors of the memory cell strings and insulating regions are formed as air gaps between the first selection transistors of the adjacent memory cell strings.

That which is claimed: 
     
       1. A vertical structure non-volatile memory device comprising:
 a stacked structure on a substrate, the stacked structure comprising stacks of conductive layers and interlayer insulating layers alternately stacked one on top of the other; 
 a plurality of semiconductor regions within a plurality of holes vertically extending through the stacked structure, the plurality of holes being spaced apart from one another in a first direction and a second direction intersecting the first direction; and 
 a plurality of cut regions passing through at least one of the conductive layers along a third direction vertical to the first and second directions and extending along the second direction between the plurality of holes, the plurality of cut regions comprising:
 at least one first cut region passing through the full thickness of the stacked structure to the substrate and being occupied by a metal layer; and 
 at least one second cut region partially passing through the stacked structure from a top of the stacked structure and being occupied by an air gap, the air gap extending parallel with the metal layer. 
 
 
     
     
       2. The vertical structure non-volatile memory device of  claim 1 , wherein the air gap has a horizontal length in the first direction and a vertical length greater than the horizontal length in the third direction. 
     
     
       3. The vertical structure non-volatile memory device of  claim 1 , wherein the conductive layers of the stacked structure comprise:
 a first memory cell gate between the substrate and the air gap; 
 a first selection transistor gate on the first memory cell gate; 
 a second memory cell gate integrally connected to the first memory cell gate between the substrate and the air gap; and 
 a second selection transistor gate on the second memory cell gate, the second selection transistor gate being spaced apart from the first selection transistor gate with the air gap interposed therebetween. 
 
     
     
       4. The vertical structure non-volatile memory device of  claim 1 , wherein the at least one first cut region comprises a pair of first cut regions, and the air gap is between the pair of first cut regions. 
     
     
       5. The vertical structure non-volatile memory device of  claim 4 , further comprising a first memory cell string and a second memory cell string vertically extending between the pair of first cut regions,
 wherein the conductive layers of the stacked structure comprise: 
 a first memory cell gate of the first memory cell string; 
 a first selection transistor gate of the first memory cell string, the first selection transistor gate formed on the first memory cell gate; 
 a second memory cell gate of the second memory cell string, the second memory cell gate being integrally connected to the first memory cell gate; and 
 a second selection transistor gate of the second memory cell string, the second selection transistor gate being spaced apart from the first selection transistor gate with the air gap interposed therebetween. 
 
     
     
       6. The vertical structure non-volatile memory device of  claim 5 , wherein the conductive layers of the stacked structure further comprise:
 a third selection transistor gate disposed between the first memory cell gate and the first selection transistor gate; and 
 a fourth selection transistor gate disposed between the second memory cell gate and the second selection transistor gate, the fourth selection transistor gate being spaced apart from the third selection transistor gate with the air gap interposed therebetween. 
 
     
     
       7. The vertical structure non-volatile memory device of  claim 1 , wherein the plurality of cut regions comprises a plurality of first cut regions and a plurality of second cut regions, and
 wherein the plurality of first cut regions and the plurality of second cut regions are alternately disposed one after the other along the first direction. 
 
     
     
       8. The vertical structure non-volatile memory device of  claim 1 , wherein the substrate comprises an impurity region extending in the second direction between the plurality of semiconductor regions, and
 wherein the metal layer is formed on the impurity region. 
 
     
     
       9. A vertical structure non-volatile memory device comprising:
 a stacked structure on a substrate, the stacked structure comprising stacks of conductive layers and interlayer insulating layers alternately stacked one on top of the other; 
 a pair of first cut regions passing through the full thickness of the stacked structure to the substrate and being occupied by a metal layer, the pair of first cut regions being spaced apart from each other in a first direction; 
 a second cut region partially passing through the stacked structure from a top of the stacked structure between the pair of first cut regions and being occupied by an air gap; and 
 a plurality of semiconductor regions vertically extending through the stacked structure, and being spaced apart from one another in the first direction and a second direction intersecting the first direction, the plurality of semiconductor regions comprising a first series of semiconductor regions arrayed between one of the pair of first cut regions and the second cut region, and a second series of semiconductor regions arrayed between the other of the pair of first cut regions and the second cut region. 
 
     
     
       10. The vertical structure non-volatile memory device of  claim 9 , wherein the air gap and the metal layer are parallel with each other. 
     
     
       11. The vertical structure non-volatile memory device of  claim 9 , wherein the pair of first cut regions and the second cut region extend in the second direction with the plurality of semiconductor regions interposed therebetween. 
     
     
       12. The vertical structure non-volatile memory device of  claim 9 , further comprising an insulating layer formed on sidewalls of the metal layer within each of the pair of first cut regions. 
     
     
       13. The vertical structure non-volatile memory device of  claim 9 , wherein the air gap has a horizontal length in the first direction and a vertical length greater than the horizontal length in a third direction parallel to a longitudinal direction of the semiconductor regions. 
     
     
       14. The vertical structure non-volatile memory device of  claim 9 , wherein the substrate comprises an impurity region extending in the second direction under the metal layer, and being in ohmic contact with the metal layer. 
     
     
       15. The vertical structure non-volatile memory device of  claim 9 , wherein the conductive layers of the stacked structure comprise:
 a plurality of memory cell gates between the substrate and the air gap; and 
 a pair of selection transistor gates on the a plurality of memory cell gates, the pair of selection transistor gates being spaced apart from each other with the air gap interposed therebetween. 
 
     
     
       16. A vertical structure non-volatile memory device comprising:
 a substrate having a plurality of impurity regions spaced apart from each other in a first direction and extending in a second direction intersecting the first direction; 
 a stacked structure on the substrate, the stacked structure comprising stacks of conductive layers and interlayer insulating layers alternately stacked one on top of the other; 
 a plurality of semiconductor regions vertically extending through the stacked structure, the plurality of semiconductor regions being spaced apart from one another in the first direction and the second direction; 
 a plurality of first cut regions passing through the conductive layers to the impurity regions between the plurality of semiconductor regions, each of the plurality of first cut regions being occupied by a metal layer extending in the second direction; and 
 a plurality of second cut regions passing through at least one of the conductive layers between the plurality of semiconductor regions and being occupied by an air gap extending in the second direction. 
 
     
     
       17. The vertical structure non-volatile memory device of  claim 16 , wherein the plurality of first cut regions and the plurality of second cut regions are alternately disposed in the first direction. 
     
     
       18. The vertical structure non-volatile memory device of  claim 16 , wherein the air gap has a horizontal length in the first direction and a vertical length greater than the horizontal length in a third direction parallel to a longitudinal direction of the semiconductor regions. 
     
     
       19. The vertical structure non-volatile memory device of  claim 16 , wherein the conductive layers of the stacked structure comprise:
 a first memory cell gate surrounding a first semiconductor region from among the plurality of semiconductor regions between the substrate and the air gap; 
 a first selection transistor gate surrounding the first semiconductor region on the first memory cell gate; 
 a second memory cell gate integrally connected to the first memory cell gate, the second memory cell gate surrounding a second semiconductor region from among the plurality of semiconductor regions between the substrate and the air gap; and 
 a second selection transistor gate surrounding the second semiconductor region on the second memory cell gate, the second selection transistor gate being spaced apart from the first selection transistor gate with the air gap interposed therebetween. 
 
     
     
       20. The vertical structure non-volatile memory device of  claim 19 , wherein the conductive layers of the stacked structure further comprise:
 a third selection transistor gate surrounding the first semiconductor region between the first memory cell gate and the first selection transistor gate; and 
 
       a fourth selection transistor gate surrounding the second semiconductor region between the second memory cell gate and the second selection transistor gate, the fourth selection transistor gate being spaced apart from the third selection transistor gate with the air gap interposed therebetween.