Multi-fin finFETs with merged-fin source/drains and replacement gates

Abstract

A semiconductor structure including semiconductor fins, a gate over a middle portion of the semiconductor fins, and faceted semiconductor regions outside of the gate separated from gaps may be formed. The semiconductor structure may be formed by forming fins on a semiconductor substrate where each fin has a pair of sidewalls aligned parallel to the length of the fin, growing dummy semiconductor regions on the sidewalls of the fins, forming a sacrificial gate that covers a center portion of the fins and the dummy semiconductor regions, removing portions of the dummy semiconductor regions not covered by the sacrificial gate, and growing faceted semiconductor regions on the sidewalls of the portions of the fins not covered by the sacrificial gate. The faceted semiconductor regions may intersect to form gaps between the faceted semiconductor regions and the gate.

The invention claimed is: 
     
       1. A semiconductor structure comprising:
 semiconductor fins; 
 a gate over a center portion of the semiconductor fins; and 
 faceted semiconductor regions between the semiconductor fins outside of the gate, 
 wherein gaps exist between the faceted semiconductor regions and the gate so that the faceted semiconductor regions do not directly contact the gate, 
 wherein uppermost surfaces of the faceted semiconductor regions are in parallel with uppermost surfaces of the semiconductor fins. 
 
     
     
       2. The semiconductor structure of  claim 1 , further comprising:
 a dielectric layer covering the semiconductor fins, wherein the dielectric layer fills the gaps between the faceted semiconductor regions and the gate. 
 
     
     
       3. The semiconductor structure of  claim 2 , wherein the dielectric layer is in direct contact with the faceted semiconductor regions and the gate. 
     
     
       4. The semiconductor structure of  claim 1 , wherein the faceted semiconductor regions comprise silicon-germanium or carbon-doped silicon. 
     
     
       5. The semiconductor structure of  claim 1 , wherein the semiconductor fins are on top of an insulator. 
     
     
       6. A semiconductor structure comprising:
 first and second semiconductor fins on an insulator; 
 a gate over center portions of the first and second semiconductor fins; and 
 faceted semiconductor regions, one of which is in direct contact with a sidewall of an end portion of the first semiconductor fin and another one of which is in direct contact with a sidewall of an end portion of the second semiconductor fin, wherein the faceted semiconductor regions respectively extend from sidewalls of the end portions of the first and second semiconductor fins, and the faceted semiconductor regions do not contact the gate; and 
 faceted dielectric regions located between the end portions of the first and second semiconductor fins and in direct contact with the gate and the faceted semiconductor regions, 
 wherein uppermost surfaces of the faceted semiconductor regions are in parallel with uppermost surfaces of the first and second semiconductor fins. 
 
     
     
       7. The semiconductor structure of  claim 6 , wherein the faceted semiconductor regions are in direct contact with each other. 
     
     
       8. The semiconductor structure of  claim 6 , wherein the faceted semiconductor regions includes at least one same material as each of the first and second semiconductor fins. 
     
     
       9. The semiconductor structure of  claim 6 , wherein the faceted semiconductor regions comprise silicon germanium. 
     
     
       10. The semiconductor structure of  claim 6 , wherein the faceted semiconductor regions comprise silicon carbon. 
     
     
       11. The semiconductor structure of  claim 6 , further comprising:
 a gate dielectric layer in direct contact with a covering the center portions of the first and second semiconductor fins, the gate dielectric layer is located between the gate and each of the first and second semiconductor fins and separates the gate from the first and second semiconductor fins. 
 
     
     
       12. The semiconductor structure of  claim 6 , further comprising:
 a gate dielectric layer in direct contact with a covering the center portions of the first and second semiconductor fins. 
 
     
     
       13. A semiconductor structure comprising:
 first and second semiconductor fins over an insulator; 
 a gate above and between center portions of the first and second semiconductor fins; 
 merged source drain regions comprising a first end portion of the first semiconductor fin, a second end portion of the second semiconductor fin, and faceted semiconductor regions, wherein one of the faceted semiconductor regions is in direct contact with a sidewall of the first end portion, another one of the faceted semiconductor regions is in direct contact with a sidewall of the second end portion, the faceted semiconductor regions respectively extend between the sidewalls of first and second end portions, and the faceted semiconductor regions do not contact the gate; and 
 faceted dielectric regions located between the first and second end portions and in direct contact with the gate and the faceted semiconductor regions, 
 wherein uppermost surfaces of the faceted semiconductor regions are in parallel with uppermost surfaces of the first and second semiconductor fins. 
 
     
     
       14. The semiconductor structure of  claim 13 , wherein the faceted semiconductor regions includes at least one same material as each of the first and second semiconductor fins. 
     
     
       15. The semiconductor structure of  claim 13 , wherein the faceted semiconductor regions comprise silicon germanium. 
     
     
       16. The semiconductor structure of  claim 13 , wherein the faceted semiconductor regions comprise silicon carbon. 
     
     
       17. The semiconductor structure of  claim 13 , further comprising:
 a gate dielectric layer in direct contact with a covering the center portions of the first and second semiconductor fins, the gate dielectric layer is located between the gate and each of the first and second semiconductor fins and separates the gate from the first and second semiconductor fins. 
 
     
     
       18. The semiconductor structure of  claim 13 , further comprising:
 a gate dielectric layer in direct contact with a covering the center portions of the first and second semiconductor fins.