Method and system of collective failure diagnosis for multiple electronic circuits

Abstract

In order to detect and locate defects, or faults, in a plurality of chips or other circuits sharing a common design, said chips are each tested for incorrect outputs, or failures, in response to inputs. The incorrect outputs are then collectively diagnosed in a single simulation by simulating a series of suspected fault candidates on a simulated chip of the chip design, and afterward comparing the incorrect outputs generated by each fault candidate to the incorrect outputs of the individual chips, to determine if a fault candidate generates all failures for a chip and no others. The test inputs and expected outputs may be predetermined through Automatic Test Pattern Generation. The fault candidates may be determined by use of a backtrace process such as back cone tracing. The failures may be recorded in association with a measure point, the input pattern that resulted in the failure, and the failure value.

What is claimed is: 
     
       1. A method of detecting and diagnosing failures and faults in a plurality of chips implementing a common design, the method comprising:
 for each chip in the plurality of chips:
 receiving, by a chip failure detection device, one or more input patterns of one or more inputs predetermined under a testing scheme predetermined for the common design of the plurality of chips, the testing scheme including an expected output pattern of one or more expected outputs for each input pattern, 
 for each supplied input pattern, capturing a resulting output pattern and comparing the resulting output pattern with the expected output pattern, and 
 for each resulting output pattern that does not match the expected output pattern, recording one or more real failures, each real failure representing at least one unexpected output of the resulting output pattern and recorded in association with the chip and the input pattern; 
 
 generating, in a chip modeling module, a simulated chip model having the common design of the plurality of chips; 
 running, in a chip simulation module using the simulated chip model, a simulation, in which the one or more input patterns are applied in the simulation to each of a plurality of simulated faults, and each simulated unexpected output pattern resulting from a simulated input pattern and a simulated fault is recorded as one or more simulated failures, each simulated failure representing at least one unexpected output of the simulated unexpected output pattern and recorded in association with the simulated input pattern and the simulated fault; 
 for each simulated fault, compiling a simulation report including all simulated failures associated with the simulated fault; and 
 for each chip in the plurality of chips,
 compiling a chip failure report including all real failures associated with the chip, 
 for each simulated fault, comparing the real failures of the chip failure report to the simulated failures of the simulation report of the simulated fault, and 
 generating a chip diagnosis report including at least one result of the comparison. 
 
 
     
     
       2. The method of  claim 1 , wherein at least one of the one or more input patterns applied in the simulation is a supplied input pattern for which the resulting output pattern matched the expected output pattern for all chips in the plurality of chips. 
     
     
       3. The method of  claim 1 , wherein each chip diagnosis report includes all simulated faults for which a set of all simulated failures of the simulation report of the simulated fault matches a set of all real failures of the chip failure report. 
     
     
       4. The method of  claim 1 , wherein each chip diagnosis report includes all simulated faults for which a set of all simulated failures of the simulation report of the simulated fault form a subset of a set of all real failures of the chip failure report. 
     
     
       5. The method of  claim 1 , further comprising, before generating the simulated chip model, organizing the plurality of chips into one or more groups of chips, each chip group formed based on a commonality of failures. 
     
     
       6. The method of  claim 1 ,
 wherein each real failure represents exactly one unexpected output of the resulting output pattern, and all unexpected outputs of each non-matching resulting output pattern are so recorded, and 
 wherein each simulated failure represents exactly one simulated unexpected output, and all simulated unexpected outputs are so recorded. 
 
     
     
       7. The method of  claim 1 , wherein each of the plurality of simulated faults are determined by conducting a back cone trace according to one of the unexpected outputs of the one or more recorded real failures. 
     
     
       8. The method of  claim 1 ,
 wherein, for each resulting output pattern that does not match the expected output pattern, one real failure is recorded for each unexpected output of the resulting output pattern, and 
 wherein each real or simulated failure associated with a combination of measure point and input pattern which is unique among all real or simulated failures is assigned a unique failure index. 
 
     
     
       9. The method of  claim 8 ,
 wherein a data representation of the simulation report includes an array of failure bits, each failure bit having a bit index, each failure bit set to a bit value of 1 if and only if the simulated failure having the failure index corresponding to the bit index of the failure bit is associated with the simulated fault. 
 
     
     
       10. A non-transitory computer readable medium encoded with executable processing instructions for implementing the method of  claim 1  using one or more processors. 
     
     
       11. A failure diagnosis system for chips, the system comprising:
 a chip failure detection device including a chip receptacle, one or more processors, and one or more data storage units, the chip receptacle having input and output connectors, the one or more processors configured to:
 supply one or more input patterns of one or more inputs through the input connector to a chip installed in the chip receptacle, the one or more input patterns predetermined under a testing scheme for the chip design of the chip, the testing scheme including an expected output pattern of one or more outputs for each input pattern, the testing scheme stored in one of the one or more data storage units, 
 for each supplied input pattern, capture a resulting output pattern from the output connector of the chip receptacle and compare it with the expected output pattern, and 
 for each resulting output pattern that does not match the expected output pattern, recording one or more real failures to one of the one or more data storage units, each real failure representing at least one unexpected output of the resulting output pattern and recorded in association with the chip and the input pattern, 
 
 a chip modeling module configured to generate a simulated chip model having a predetermined chip design; 
 a chip simulation module configured to:
 receive, from the chip modeling module, the simulated chip model, 
 run a simulation, using the simulated chip model, in which one or more input patterns are applied in the simulation to each of a plurality of simulated faults, and 
 record each simulated unexpected output resulting from a simulated input pattern and a simulated fault as a simulated failure, in association with the simulated input pattern and the simulated fault, 
 
 a chip reporting module configured to:
 receive, from the chip simulation module, the set of recorded simulated failures, 
 receive one or more chip failure reports, each chip failure report identifying a chip presently or previously installed in the chip receptacle, and a set of failures associated with said chip, 
 for each simulated fault, comparing the real failures of the chip failure report to the simulated failures of the simulation report of the simulated fault, and 
 generate a chip diagnosis report including at least one result of the comparison. 
 
 
     
     
       12. The system of  claim 11 ,
 wherein the chip failure report is compiled by the one or more processors and includes all real failures associated with the chip identified in the chip failure report, and 
 the chip reporting module receives the one or more chip failure reports from the chip fault detection device. 
 
     
     
       13. The system of  claim 11 ,
 wherein the chip failure report is compiled by the one or more processors and includes all real failures associated with the chip identified in the chip failure report, 
 the chip modeling module receives the one or more chip failure reports from the chip fault detection device, and 
 the chip reporting module receives the one or more chip failure reports from the chip fault detection device. 
 
     
     
       14. The system of  claim 11 , wherein each of the plurality of simulated faults are determined by the chip modeling module conducting a back cone trace according to one of the recorded real failures. 
     
     
       15. The system of  claim 11 , wherein each of the plurality of simulated faults are determined by the chip simulation module conducting a back cone trace according to one of the recorded real failures. 
     
     
       16. The system of  claim 11 , wherein the chip modeling module, the chip simulation module, and the chip reporting module are encoded as software on the data storage units and executed on the one or more processors.