Bang-bang time to digital converter systems and methods

Abstract

A time to digital converter includes a mutual exclusion element and a sampling component. The mutual exclusion element is configured to receive a first clock and a second clock and to generate a first pulse and a second pulse. The mutual exclusion element is configured to drive the first pulse to a first logic state and the second pulse to a second logic state upon the first clock being earlier than the second clock and drive the second pulse to the first logic state and the first pulse to the second logic state upon the second clock being earlier than the first clock. The sampling component is configured to receive the first pulse and the second pulse and to generate a decision signal according to the first pulse and the second pulse.

What is claimed is: 
     
       1. A time to digital converter comprising:
 a mutual exclusion element configured to receive a first clock and a second clock and to generate a first pulse and a second pulse, wherein the mutual exclusion element is configured to drive the first pulse to a first logic state and the second pulse to a second logic state upon the first clock being earlier than the second clock and drive the second pulse to the first logic state and the first pulse to the second logic state upon the second clock being earlier than the first clock; and 
 a sampling component configured to receive the first pulse and the second pulse and to generate a decision signal according to the first pulse and the second pulse, 
 wherein the decision signal includes a first early indicator and a second early indicator, wherein the first early indicator is set to the first logic state upon the first clock being earlier than the second clock and the second early indicator is set to the first logic state upon the second clock being earlier than the first clock. 
 
     
     
       2. The converter of  claim 1 , further comprising a component configured to adjust timing of at least one of the first clock and the second clock according to the decision signal. 
     
     
       3. The converter of  claim 1 , further comprising a first path configured to generate the first clock having a first delay and a second path configured to generate the second clock having a second delay. 
     
     
       4. The converter of  claim 1 , wherein the decision signal has relaxed timing. 
     
     
       5. The converter of  claim 1 , wherein the first clock and the second clock have different frequencies. 
     
     
       6. The converter of  claim 1 , wherein the first clock has a frequency at least 10 times greater than a frequency of the second clock. 
     
     
       7. The converter of  claim 1 , wherein the mutual exclusion element is configured to generate the first pulse and the second pulse based on a selected sample period. 
     
     
       8. The converter of  claim 1 , wherein the sampling component is configured to widen the states from the first pulse and the second pulse into the decision signal. 
     
     
       9. A time to digital converter comprising:
 a mutual exclusion element configured to receive a first clock and a second clock and to generate a first pulse and a second pulse, wherein the mutual exclusion element is configured to drive the first pulse to a first logic state and the second pulse to a second logic state upon the first clock being earlier than the second clock and drive the second pulse to the first logic state and the first pulse to the second logic state upon the second clock being earlier than the first clock; and 
 a sampling component configured to receive the first pulse and the second pulse and to generate a decision signal according to the first pulse and the second pulse, 
 wherein the mutual exclusion element includes cross coupled NAND gates and a metastability filter coupled to the cross coupled NAND gates. 
 
     
     
       10. The converter of  claim 9 , wherein an output of a first NAND gate is driven to the first state and an output of a second NAND gate is driven to the second state upon the first clock being earlier than the second clock. 
     
     
       11. A time to digital converter comprising:
 a mutual exclusion element configured to receive a first clock and a second clock and to generate a first pulse and a second pulse, wherein the mutual exclusion element is configured to drive the first pulse to a first logic state and the second pulse to a second logic state upon the first clock being earlier than the second clock and drive the second pulse to the first logic state and the first pulse to the second logic state upon the second clock being earlier than the first clock; and 
 a sampling component configured to receive the first pulse and the second pulse and to generate a decision signal according to the first pulse and the second pulse, 
 wherein the sampling component includes a first stage of delay flops and a second stage of delay flops. 
 
     
     
       12. A digital frequency system comprising:
 a first path having a first delay and configured to generate a first clock, the first clock having a first frequency; 
 a second path having a second delay and configured to generate a second clock, the second clock having a second frequency; 
 a time to digital converter configured to generate a decision signal based on the first clock and the second clock, wherein the decision signal indicates which of the first clock and the second clock is earlier; and 
 a loop component configured to receive the decision signal and generate a calibration signal based on the decision signal. 
 
     
     
       13. The system of  claim 12 , wherein the second path is configured to adjust the second clock according to the calibration signal. 
     
     
       14. The system of  claim 12 , wherein the first path and the second path are configured to adjust the first clock and the second clock according to the calibration signal. 
     
     
       15. The system of  claim 12 , wherein the loop component includes a loop filter and a low dropout regulator. 
     
     
       16. The system of  claim 12 , wherein the loop component is a multiplying delay locked loop. 
     
     
       17. A method of generating a timing decision signal, the method comprising:
 generating a first clock signal by a first path; 
 generating a second clock signal by a second path; 
 generating a first pulse and a second pulse by a mutual exclusion element, wherein the first pulse is set to a first logic state upon the first clock signal being earlier and the second pulse is set to the first logic state upon the second clock signal being earlier; and 
 generating a decision signal by a sampling component indicating which of the first and second clocks is earlier based on the first pulse and the second pulse. 
 
     
     
       18. The method of  claim 17 , further comprising adjusting a timing of the second clock signal based on the decision signal. 
     
     
       19. The method of  claim 17 , wherein the decision signal includes a first indicator set to the first state upon the first clock being earlier and a second indicator set to the first state upon the second clock being earlier.