NAND-connected string of transistors having the electrical channel in a direction perpendicular to a surface of the substrate

Abstract

Vias are formed within a stack of alternating active and insulating layers by forming a first sub stack, a second sub stack over the first sub stack, a first buffer layer therebetween and a second buffer layer under the first sub stack. An upper layer of the first sub stack is exposed through a set of vias by first and second etching processes. The first etching process forms a first set of etch vias through the second sub stack and stops at or in the first buffer layer. The second etching process etches through the first buffer layer to the upper layer of the first sub stack. A third etching process etches through the first set of etch vias, through the first sub stack and stops at or in the second buffer layer. A fourth etching process and etches through the second buffer layer.

What is claimed is:   
     
       1. A circuit, comprising:
 a substrate; and 
 a NAND-connected string of transistors on the substrate, including:
 a plurality of first nonvolatile memory cells having a first gate length; and 
 a plurality of second nonvolatile memory cells having a second gate length greater than the first gate length, 
 
 wherein the NAND-connected string has an electrical channel through the transistors of the NAND-connected string, the electrical channel having a direction perpendicular to a surface of the substrate. 
 
     
     
       2. The circuit of  claim 1 , further comprising:
 circuitry controlling the NAND-connected string, the circuitry configured to apply different pass voltages to the plurality of first nonvolatile memory cells and the plurality of second nonvolatile memory cells. 
 
     
     
       3. The circuit of  claim 1 , further comprising:
 circuitry controlling the NAND-connected string, wherein the first gate length is less than 1 micron and the second gate length is greater than 1 micron. 
 
     
     
       4. The circuit of  claim 1 , wherein the NAND-connected string comprises a GSL transistor and an SSL transistor. 
     
     
       5. The circuit of  claim 1 , wherein the NAND-connected string of transistors comprises stacks of the transistors, one of said stacks including a plurality of substrings, each of the substrings including multiple ones of the first plurality of nonvolatile memory cells connected in series, different ones of the substrings connected in series by at least one second nonvolatile memory cell of said plurality of second nonvolatile memory cells. 
     
     
       6. The circuit of  claim 5 , wherein each stack has the same number of first nonvolatile memory cells. 
     
     
       7. The circuit of  claim 5 , wherein the NAND-connected string of transistors comprises a GSL transistor and an SSL transistor. 
     
     
       8. The circuit of  claim 1 , wherein the second nonvolatile memory cells comprise an active buffer layer surrounding a trapping structure layer, the trapping structure layer surrounding a channel layer, the channel layer surrounding an insulating core. 
     
     
       9. A circuit, comprising:
 a substrate; and 
 a NAND-connected string of transistors on the substrate, including:
 a plurality of nonvolatile memory cells having a first gate length; and 
 a plurality of transistors having a second gate length greater than the first gate length; 
 
 wherein the NAND-connected string has an electrical channel through the transistors of the NAND-connected string, the electrical channel having a direction perpendicular to a surface of the substrate. 
 
     
     
       10. The circuit of  claim 9 , further comprising:
 circuitry controlling the NAND-connected string, the circuitry configured to apply different pass voltages to the plurality of nonvolatile memory cells and the plurality of transistors. 
 
     
     
       11. The circuit of  claim 9 , further comprising:
 circuitry controlling the NAND-connected string, wherein the first gate length is less than 1 micron and the second gate length is greater than 1 micron. 
 
     
     
       12. The circuit of  claim 9 , wherein the NAND-connected string comprises a GSL transistor and an SSL transistor. 
     
     
       13. The circuit of  claim 12 , wherein the GSL transistor and the SSL transistor each have a gate length greater than said first gate length. 
     
     
       14. The circuit of  claim 12 , wherein the GSL transistor and the SSL transistor each have a gate length equal to the second gate length. 
     
     
       15. The circuit of  claim 9 , wherein the NAND-connected string of transistors comprises stacks of the transistors, one of said stacks including a plurality of substrings, each of the substrings including multiple ones of the plurality of nonvolatile memory cells connected in series, different ones of the substrings connected in series by at least one of said plurality of transistors. 
     
     
       16. The circuit of  claim 15 , wherein each stack has the same number of nonvolatile memory cells. 
     
     
       17. The circuit of  claim 15 , wherein the NAND-connected string of transistors comprises a GSL transistor and an SSL transistor. 
     
     
       18. The circuit of  claim 9 , wherein the transistors comprise an active buffer layer surrounding a trapping structure layer, the trapping structure layer surrounding a channel layer, the channel layer surrounding an insulating core.