Semiconductor assemblies with multi-level substrates and associated methods of manufacturing

Abstract

Various embodiments of semiconductor assemblies with multi-level substrates and associated methods of manufacturing are described below. In one embodiment, a substrate for carrying a semiconductor die includes a first routing level, a second routing level, and a conductive via between the first and second routing levels. The conductive via has a first end proximate the first routing level and a second end proximate the second routing level. The first routing level includes a terminal and a first trace between the terminal and the first end of the conductive via. The second routing level includes a second trace between the second end of the conductive via and a ball site. The terminal of the first routing level and the ball site of the second routing level are both accessible for electrical connections from the same side of the substrate.

We claim: 
     
       1. A method of processing a substrate for carrying a semiconductor die, comprising:
 forming a first routing level carried by a first non-conductive core; 
 forming a second routing level carried by a second non-conductive core; 
 generally aligning the first routing level relative to the second routing level; 
 fixing the first and second non-conductive cores relative to each other; and 
 forming a conductive via between the first and second routing levels, the conductive via having a first end proximate the first routing level and a second end proximate the second routing level, wherein:
 the first routing level includes a terminal and a first trace electrically connected between the terminal and the first end of the conductive via; 
 the second routing level includes a second trace electrically connected between the second end of the conductive via and a ball site; and 
 the terminal and the ball site are both accessible from the same side of the substrate. 
 
 
     
     
       2. The method of  claim 1  wherein forming the first routing level includes stripping a first conductive material from a first side of the first non-conductive core and patterning and selectively removing a portion of a second conductive material on a second side of the first non-conductive core. 
     
     
       3. The method of  claim 1  wherein forming the second routing level includes:
 stripping a first conductive material from a first side of the second non-conductive core and patterning and selectively removing a portion of a second conductive material on a second side of the second non-conductive core; and 
 depositing a solder mask on the patterned second conductive material. 
 
     
     
       4. The method of  claim 1  wherein forming the second routing level includes:
 stripping a first conductive material from a first side of the second non-conductive core and patterning and selectively removing a portion of a second conductive material on a second side of the second non-conductive core; 
 depositing a solder mask on the patterned second conductive material; and 
 forming ball pads on the second conductive material by selectively removing the deposited solder mask. 
 
     
     
       5. The method of  claim 1 , further comprising forming an opening through the first and second routing levels after generally aligning the first routing level to the second routing level. 
     
     
       6. The method of  claim 1  wherein forming the first routing level includes forming a first routing level that does not include any ball site. 
     
     
       7. The method of  claim 1  wherein fixing the first and second non-conductive cores relative to each other includes bonding the first routing level to a surface of the second non-conductive core. 
     
     
       8. The method of  claim 1  wherein the first and second routing levels and the conductive via form a substrate, and wherein the method further comprises:
 mounting a semiconductor die to the substrate; and 
 electrically connecting the semiconductor die to the first routing level. 
 
     
     
       9. The method of  claim 1  wherein the first and second routing levels and the conductive via form a substrate, and wherein the method further comprises:
 forming an opening in the substrate; 
 mounting a semiconductor die to the substrate; and 
 wirebonding the semiconductor die to the terminal of the first routing level first routing level by passing a bond wire through the opening. 
 
     
     
       10. A method of processing a substrate for carrying a semiconductor die, comprising:
 forming a first routing level on a first substrate; 
 forming a second routing level on a second substrate different than the first substrate; 
 generally aligning the first routing level relative to the second routing level; 
 joining the first and second substrates before forming a conductive via; and 
 forming the conductive via between the first and second routing levels, the conductive via having a first end proximate the first routing level and a second end proximate the second routing level, wherein:
 the first routing level includes a terminal and a first trace electrically connected between the terminal and the first end of the conductive via; 
 the second routing level includes a second trace electrically connected between the second end of the conductive via and a ball site; and 
 the terminal and a ball site are both accessible from the same side of the substrate. 
 
 
     
     
       11. The method of  claim 10 , further comprising:
 mounting a semiconductor die to the first substrate; 
 forming an opening at least through the first substrate, the opening exposing a bond site on the semiconductor die; and 
 electrically connecting the bond site to the terminal through the opening. 
 
     
     
       12. The method of  claim 11 , further comprising attaching a wirebond to the terminal and a solder ball to the pad. 
     
     
       13. The method of  claim 10 , further comprising forming an opening through the second substrate before joining the first and second substrates, wherein the terminal is exposed through the opening. 
     
     
       14. The method of  claim 10 , further comprising:
 forming a first opening through the second substrate before joining the first and second substrates; and 
 forming a second opening through the first substrate after joining the first and second substrates, wherein the second opening is aligned with the first opening. 
 
     
     
       15. The method of  claim 10  wherein the first routing level is formed on a first side of the first substrate, and wherein the method further comprises:
 stripping a conductive material from a surface on a second side of the first substrate opposite the first side; and 
 attaching a semiconductor die to at least a portion of the surface. 
 
     
     
       16. The method of  claim 10 , further comprising stripping a conductive material from a surface of the second substrate, and wherein joining the first and second substrates includes attaching the first substrate to at least a portion of the surface. 
     
     
       17. A method for manufacturing a semiconductor assembly, the method comprising:
 patterning a first conductive material to define a first trace and a terminal connected to the first trace, wherein the first conductive material is carried by a first non-conductive core; 
 patterning a second conductive material to define a second trace and a pad connected to the second trace, wherein the second conductive material is carried by a second non-conductive core; 
 attaching the second non-conductive core to at least a portion of the first trace and a surface of the first non-conductive core; 
 forming a conductive via at least through the second non-conductive core, wherein the conductive via electrically connects the first trace with the second trace; and 
 forming an opening at least through the second non-conductive core to expose the terminal through the opening. 
 
     
     
       18. The method of  claim 17  wherein:
 the surface of the first non-conductive core is at a first side of the first non-conductive core; 
 the opening extends through the first non-conductive core; and 
 the method further comprises attaching a semiconductor die to a surface of the first non-conductive core at a second side of the first non-conductive core opposite the first side, wherein a portion of the semiconductor die is exposed through the opening. 
 
     
     
       19. The method of  claim 17  wherein the opening is a first opening, and wherein the method further comprises forming a second opening through the first non-conductive core and adjacent the first opening. 
     
     
       20. The method of  claim 19 , further comprising attaching a semiconductor die to the first non-conductive core, wherein a portion of the semiconductor die is exposed through the first and second openings.