Dynamic LED display screen with increased frequency of input clock signals

Abstract

A PWM circuit is disclosed in the application, which includes: a PWM counter, a reference value setting register, a frequency multiplier and a comparator, where the frequency multiplier is adapted to increase the frequency of a clock signal input and to output the clock signal with the increased frequency to the PWM counter. An LED drive circuit is further disclosed in the application. The frequency of a PWM input clock signal is increased to N times of the original frequency of the PWM input clock signal by the frequency multiplier, so that the counting cycle of the PWM counter is shortened to 1/N of the original counting cycle of the PWM counter. Therefore, in the dynamic LED display screen, the refresh frequency can be increased to N times of the original refresh frequency while the original resolution is maintained.

The invention claimed is: 
     
       1. A dynamic LED display screen, comprising:
 a PWM circuit comprising a PWM counter, adapted to count a clock signal; a reference value setting register, adapted to set a comparison reference value which determines the duty cycle of a PWM signal; a frequency multiplier, adapted to increase frequency of an clock signal input and to output clock signal with the increased the frequency to the PWM counter; and a comparator, adapted to generate a PWM signal based on a comparison between the comparison reference value and the count value of the PWM counter; 
 an LED light source; and 
 a drive module connected between the PWM circuit and the LED light source, for supplying stable current to the LED light source, wherein the display screen is a dynamic LED display screen. 
 
     
     
       2. The dynamic LED display screen drive circuit according to  claim 1 , wherein the frequency multiplier is one of a transistor frequency multiplier, a varactor diode frequency multiplier, a step recovery diode frequency multiplier, a ferrite frequency multiplier, a phase-locked loop frequency multiplier and a synchronous frequency multiplier. 
     
     
       3. The dynamic LED display screen drive circuit according to  claim 1 , wherein the PWM circuit further comprises a count value upper-limit setting register, for setting a count value upper-limit which determines the pulse width of the PWM signal in the PWM counter. 
     
     
       4. The dynamic LED display screen drive circuit according to  claim 1 , wherein the comparator is adapted to output an low level as the PWM signal when the count value of the PWM counter is lower than the comparison reference value, and to output an “H” level as the PWM signal when the count value of the PWM counter is higher than the comparison reference value. 
     
     
       5. The dynamic LED display screen drive circuit according to  claim 1 , wherein the comparator is adapted to output an high level as the PWM signal when the count value of the PWM counter is lower than the comparison reference value, and to output an “L” level as the PWM signal when the count value of the PWM counter is higher than the comparison reference value.