US9177941B2ActiveUtilityA1
Semiconductor device with stacked semiconductor chips
Est. expiryApr 23, 2030(~3.7 yrs left)· nominal 20-yr term from priority
Inventors:Naohiro Handa
H10W 90/754H10W 90/734H10W 90/732H10W 90/701H10W 90/28H10W 74/117H10W 74/00H10W 72/5449H10W 72/5445H10W 72/951H10W 72/932H10W 72/884H10W 72/252H10W 72/0198H10W 72/075H10W 72/073H10W 72/29H10W 70/656H10W 74/016H10W 74/014H10W 70/65H10W 90/00H01L 2924/15311H01L 2924/01005H01L 2924/3862H01L 2224/131H01L 2924/014H01L 2224/32227H01L 24/83H01L 21/565H01L 2224/49175H01L 2224/83H01L 2924/01014H01L 2224/32225H01L 21/561H01L 24/49H01L 23/3128H01L 2225/0651H01L 2224/92247H01L 2924/00H01L 2924/01033H01L 2924/15184H01L 24/48H01L 2224/48235H01L 2224/32145H01L 24/85H01L 2924/01004H01L 2224/48227H01L 23/49816H01L 2225/06568H01L 25/0657H01L 23/49838H01L 2224/0401H01L 2224/48091H01L 2224/85H01L 2224/49171H01L 2224/97H01L 2924/00012H01L 2224/05599H01L 24/97H01L 2924/15787H01L 2224/73265H01L 2924/01006H01L 2924/00014
41
PatentIndex Score
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Cited by
11
References
8
Claims
Abstract
A semiconductor chip 109 is mounted on a substrate 100 , first wire group 120 and a second wire group 118 having a wire length shorter than the first wire group are provided so as to connect the substrate 100 and the semiconductor chip 109 to each other, and a sealing resin 307 is injected from the first wire group 120 toward the second wire group 118 so as to form a sealer 401 covering the semiconductor chip 109 , the first wire group 120 , and the second wire group 118.
Claims
exact text as granted — not AI-modifiedWhat is claimed is:
1. A semiconductor device comprising:
a substrate having a first side and a second side opposite the first side;
a first semiconductor chip on the substrate;
a second semiconductor chip on the first semiconductor chip, the second semiconductor chip having plural first bonding pads spaced a first distance apart along a third side of the second semiconductor chip facing the first side and plural second bonding pads spaced a second distance apart along a fourth side of the second semiconductor chip opposite the third side, the first side being spaced farther from the third side than the second side is spaced from the fourth side;
a plurality of first wires that each directly connect the substrate to respective ones of the first bonding pads, and a plurality of second wires that each directly connect the substrate to respective ones of the second bonding pads, each wire of the plurality of first wires being longer than each wire of the plurality of second wires; and
a sealing resin covering the first and second semiconductor chips, the plurality of first wires, and the plurality of second wires,
wherein the second semiconductor chip is completely overlapped with the first semiconductor chip in plan view.
2. The semiconductor device of claim 1 , wherein the second distance is greater than the first distance.
3. The semiconductor device of claim 2 , wherein a quantity of the plural first bonding pads exceeds a quantity of the plural second bonding pads.
4. The semiconductor device of claim 1 , wherein the first bonding pads are arrayed in a first line and the second bonding pads are arrayed in a second line parallel to the first line.
5. The semiconductor device of claim 1 , wherein the second semiconductor chip is smaller than the first semiconductor chip so that connection pads on the first semiconductor chip are exposed.
6. The semiconductor device of claim 1 , wherein the first semiconductor chip has a fifth side facing the first side of the substrate and a sixth side opposite the fifth side, and wherein the fifth side is spaced farther from the third side than the sixth side is spaced from the fourth side.
7. A semiconductor device comprising:
a substrate having a first side and a second side opposite the first side;
a first semiconductor chip on the substrate;
a second semiconductor chip on the first semiconductor chip, the second semiconductor chip having plural first bonding pads spaced a first distance apart along a third side of the second semiconductor chip facing the first side and plural second bonding pads spaced a second distance apart along a fourth side of the second semiconductor chip opposite the third side, the first side being spaced farther from the third side than the second side is spaced from the fourth side;
a first wire group connecting the substrate to the first bonding pads and a second wire group connecting the substrate to the second bonding pads, each wire of the first wire group being longer than each wire of the second wire group; and
a sealing resin covering the first and second semiconductor chips and the first and second wire groups,
wherein the second distance is greater than the first distance,
wherein the substrate comprises plural third bonding pads arrayed along the first side and plural fourth bonding pads arrayed along the first side closer to the first semiconductor chip than the third bonding pads, the first wire group being connected to the third bonding pads, and the fourth bonding pads being connected to the first semiconductor chip, and
wherein the substrate comprises plural fifth bonding pads arrayed along the second side and plural sixth bonding pads arrayed along the second side closer to the first semiconductor chip than the fifth bonding pads, the second wire group being connected to the fifth bonding pads, and the sixth bonding pads being connected to the first semiconductor chip.
8. The semiconductor device of claim 7 , wherein third bonding pads are spaced a third distance apart and the fifth bonding pads are spaced a fourth distance apart, the fourth distance being greater than the third distance.Join the waitlist — get patent alerts
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