Semiconductor device including latency counter

Abstract

For example, a semiconductor device includes a first latency counter, which selects whether to give an odd-cycle latency to an internal command signal; and a second latency counter, which gives a latency to an internal command signal at intervals of two cycles. The latency counters are connected in series. Since the number of bits in control information, which is used to set a latency, is smaller than the types of settable latency as a result, it is possible to reduce wiring density.

What is claimed is:  
     
       1. A method comprising:
 supplying, using one of first and second latency counters, an internal command signal to a command output line when a predetermined latency elapses after the internal command signal is supplied to the other of the first and second latency counters from a command input line; 
 selecting whether to give the internal command signal an odd-cycle latency based on first control information; and 
 based on second control information, effecting upon the internal command signal, a latency at intervals of two cycles. 
 
     
     
       2. The method as claimed in  claim 1 , wherein the predetermined latency is an integral multiple of a clock cycle of an external clock signal supplied from outside. 
     
     
       3. The method as claimed in  claim 2 , further comprising:
 latching the internal command signal in synchronization with an internal clock signal that has the same clock cycle as the external clock signal; and 
 selecting one of the internal command signal that has passed through a first register of the first latency counter and the internal command signal that has not passed through the first register. 
 
     
     
       4. The method as claimed in  claim 1 , further comprising:
 generating first and second internal clock signals each having double the clock cycle of the external clock signal, the first and second internal clock signals having different phase from each other by an amount equivalent to the clock cycle of the external clock signal, and 
 wherein the first latency counter includes:
 a first selector that outputs, based on the first control information, the internal command signal that is captured from the command input line in synchronization with one of the first and second internal clock signals; and 
 a second selector that outputs, based on the first control information, the internal command signal that is captured from the command input line in synchronization with the other of the first and second internal clock signals. 
 
 
     
     
       5. The method as claimed in  claim 1 , further comprising:
 generating the internal command signal based on an external command signal issued from outside; and 
 supplying the command input line with the internal command signal. 
 
     
     
       6. The method as claimed in  claim 1 , further comprising:
 operating, in response to the internal command signal on the command output line, a column system control circuit of a memory cell array, 
 wherein the column system control circuit controls a timing of column access to the memory cell array. 
 
     
     
       7. The method as claimed in  claim 1 , further comprising:
 employing a control circuit to read out data from a number of memory cells; and 
 responding to a signal of the command output line to output a data signal indicative of the data. 
 
     
     
       8. The method as claimed in  claim 1 , wherein the method is carried out within a single semiconductor chip. 
     
     
       9. The method as claimed in  claim 8 , wherein the single semiconductor chip is a synchronous dynamic random access memory chip.