Multi-stage parallel super-high-speed ADC and DAC of logarithmic companding law

Abstract

Multi-stage parallel super-high-speed ADC and DAC of a logarithmic companding law has a voltage follower switch having zero voltage drop, and also has a lossless threshold switch group, wherein a quantization voltage of A/D conversion or D/A conversion is directly obtained through voltage-dividing resistance thereof. The ADC and DAC simplify a conversion process and reduce a conversion error. The ADC and DAC provide multi-stage multi-bit parallel super-high-speed A/D conversion and D/A conversion with logarithmic companding law of a high conversion rate and the low conversion error.

What is claimed is: 
     
       1. Multi-stage parallel super-high-speed ADC and DAC of a logarithmic companding law, wherein the logarithmic ADDA comprises multi-sub-ADDAs, wherein at least one sub-ADDA comprises a stage-potential processing device, wherein the stage-potential processing device at stage λ comprising:
 a stage-potential generating module at stage λ which comprises a resistor chain for generating reference potential points and a potential stage determining circuit, wherein let Q=2 q , the q-bit reference potential points of the sub-ADDA at stage λ are formed by series connected Q resistors; the resistor chain of the series connected Q resistors provides Q+1 potential points V λQ , V λ(Q−1)  . . . V λ1 , V λ0 , among which V λ(Q−1)  . . . V λ1 , V λ0  are the Q step reference potential points at stage λ, wherein V λQ  is equal to a power source anode V p , and is excluded from the reference potential at step Q; let g be equal to some point whose subscript is within (0˜Q−1), point g is called a test point, and V λg  is the reference potential at step g stage λ; a quantization distance (also called a step difference) Δ λg =V λ(g+1) −V λg ; when a to-be-compared voltage U λZ  falls within a conversion range V λQ ˜0, there is always a point G correspondent to U λZ , wherein, when g=G, V λ(G+1) >U λZ >V λG  and U λZ −V λG <Δ λG ; particularly, point G is named as a stage point, and V λg  at the stage point G is the reference point which is smaller than and closest to U λZ ; V λg  is a special reference point among the reference points V λ(Q−1) −V λ0 , especially marked as V λG ; V λG  is called a stage-potential at stage λ; relative to the sub-ADDA at stage λ, the stage-potential V λG  is a conversion value of U λZ ; 
 a stage-potential extracting module, wherein, for the sub-ADDA at stage λ, although it can be determined that which of the reference potential points V λ(Q−1) ˜V λ0  is the stage-potential V λG , the stage-potential V λG  still remains to be extracted, which requires the stage-potential extracting module; the stage-potential extracting module is a stage-potential switch; a group of threshold switches forms the stage-potential switch; the stage-potential switch JDWKG λ  comprises a threshold switch group LJKGZ λ  and a multi-channel switch DLKG λ , wherein the threshold switch group is the group of the threshold switches whose output terminals are parallel connected into a common terminal and whose input terminals form an input terminal group of the threshold switch group; control characters are provided for directly choosing and connecting one of the input terminals as a strobe terminal; the threshold switch point S λg  at step g stage λ has an upper control character I λ(g+1)  and a lower control character I λg  which are respectively connected to and equal to potential comparison values I* λ(g+1)  and I* λg ; when I λ(g+1) =1 or I λg =0, the switch point S λg  is open; only when the switch point S λg  satisfies requirements of I λ(g+1) =0 and I λg =1, the switch point S λg  is connected and becomes a strobe point S λG ; a potential at the strobe point S λG  is V λG  at step G stage λ, and is also called the stage-potential V λG  of stage λ; 
 wherein the stage-potential V λG  is a bridge of A/D conversion and D/A conversion, and corresponds respectively to digital signals D λ(q−1) ˜D λ0  and the to-be-compared voltage U λZ , wherein the correspondence is accomplished via a correspondence between the reference points V λ(Q−1) ˜V λ0  and the control characters I λ(Q−1) ˜I λ0 , and a correspondence between the reference points V λ(Q−1) ˜V λ0  and the threshold switch group S λ(Q−1) ˜S λ0 ; the stage-potential V λG  is a threshold point among the reference points V λ(Q−1) ˜V λ0 , and is determined through values of the control characters I λ(Q−1) ˜I λ0  and the strobe terminal of the threshold switch group S λ(Q−1) ˜S λ0 ; 
 wherein the stage-potential V λG  is obtained through the correspondence between the reference points V λ(Q−1) ˜V λ0  and the control characters I λ(Q−1) ˜I λ0 , and the correspondence between the reference points V λ(Q−1) ˜V λ0  and the switch group S λ(Q−1) ˜S λ0 ; wherein 
 firstly, the correspondence between V λ(Q−1) ˜V λ0  and the digital signals, or the correspondence between V λ(Q−1) ˜V λ0  and the control characters I λ(Q−1) ˜I λ0  is illustrated as follows; among the reference points V λ(Q−1) ˜V λ0 , V λG  is the threshold point, when the to-be-compared voltage at stage λ U λZ >(V λG ˜V λ0 ), the control characters I λG ˜I λ0  correspondent to the reference points V λG ˜V λ0  are equal to 1; in other words, each threshold switch (S λ(G−1) ˜S λ0 ) connected below V λG  has the control character I λ(g+1) =I λg =1, so (S λ(G−1) ˜S λ0 ) are at states of OFF; when U λz <(V λQ ˜V λ(G+1) ), the control characters I λQ ˜I λ(G+1)  correspondent to the reference points V λQ ˜V λ(G+1)  are equal to zero; in other words, each threshold switch (S λ(G+1) ˜S λ(Q−1) ) connected above V λG  has the control character I λ(g+1) =I λg =0, so (S λ(G+1) ˜S λ(Q−1) ) are also at states of OFF; only when the threshold switch S λG  at the threshold point has the control characters I λ(G+1) =0 and I λG =1, S λG  is at a state of ON; and 
 secondly, V λ(Q−1) ˜V λ0  and the correspondent S λ(Q−1) ˜S λ0  are connected directly, or correspondently via an arithmetic circuit; the strobe point S λG  among S λ(Q−1) ˜S λ0  extracts out the stage-potential V λG , and sends the extracted stage-potential V λG  into a main line S λ  of the stage-potential switch; the sent stage-potential V λG  and the stage output values of other sub-ADDAs are collected and calculated, for accomplishing the A/D and D/A conversions; the stage-potential V λG  is the reference point potential closest to the to-be-compared voltage U λZ ; V λG  and U λZ  have a relation of V λG =U λZ −U λx , wherein U λx  is a residue voltage which is smaller than a span of the reference point voltage; and 
 wherein the threshold switch comprises a lossy switch and a lossless switch, wherein the lossless switch comprises a voltage follower switch which functions as a signal switch for transmitting or blocking signals, wherein the voltage follower switch comprises two modules, a module of a voltage follower and a module of a power source switch; the power source switch is an electronic device provided on a power source loop of the follower; connection and disconnection of the power source loop of the follower are controlled by the power source switch through the control characters, so as to control connection and disconnection of a signal loop of the follower. 
 
     
     
       2. A lossless switch based on a follower switch, wherein the follower switch of the lossless switch functions as a signal switch for transmitting or blocking signals; the follower switch comprises two modules, a follower and a power source switch, wherein the power source switch is an electronic device provided on a power source loop of the follower, and controls connection and disconnection of the power source loop of the follower through control characters; and
 wherein the follower is at a state of following voltage when the power source loop is connected; herein the signal is inputted through a non-inverting terminal of the follower, and a voltage of an output terminal is accurately equal to a voltage of the non-inverting terminal, in such a manner that the signal is on; the follower cuts off the signal when the power source loop is disconnected; the follower switch controls the connection and disconnection of the power source loop through the control characters, so as to further control connection and disconnection of a signal loop of the follower; logic relations about the connection and disconnection of the follower switch formed by the control characters is arbitrary, comprising normally open, normally close and threshold switching; preferably, the follower switch is a threshold switch having the logic relations; the threshold switch S λg  comprises S λg1 , S λg2  and S λg3 . 
 
     
     
       3. The lossless switch based on a follower switch, as recited in  claim 2 , wherein the lossless switch S λg  is transformed from the follower switch by establishing a control logic of the power source switch; the logic comprises:
 when I λg =0 or I λ(g+1) =1, S λg  is signal off; only when I λg =1 and I λ(g+1) =0, A λg  is powered on only by closing KS 1  and KS 3  which are power source switches conducting at high potential and closing KS 0  and KS 2  which are power source switches conducting at low potential, in such manner that A λg  is signal on; otherwise, once I λg =0 or I λ(g+1) =1, KS 1  and KS 3  are cutting off, or, KS 0  and KS 2  are cutting off, in such a manner that A λg  is powered off and thus signal-off; for simplification, one of KS 0  and KS 2  is arbitrarily in short circuit; one of KS 1  and KS 3  is arbitrarily in short circuit. 
 
     
     
       4. The multi-stage parallel super-high-speed ADC and DAC of the logarithmic companding law, as recited in  claim 1 , wherein an m stages*q-bit equal resistance logarithmic ADC is established as follows, wherein after being processed by a front-end circuit QZDL, an original input alternating signal u αy  becomes an input voltage at stage α U αy ; an input voltage U λy  at stage λ ranges between 0˜V p ; AD# λ  at stage λ processes the input voltage U λy  at stage λ with an AD conversion through following five modules and processes thereof:
 (1) a stage-potential V λG  generating module, wherein, let Q=2 q , a voltage-dividing resistor chain of a parallelizer at stage λ R λ(Q−1) ˜R λ0  forms potential reference points V λ(Q−1) ˜V λ0  at stage λ, wherein V λ0  is a bottom potential; the reference points V λ(Q−1) ˜V λ1  are correspondently connected to inverting terminals of comparators C λ(Q−1) ˜C λ1  in the parallelizer; the input voltage at stage λ U λy  becomes a temporarily stable voltage U* λy  through sampling and holding; then summing the bottom potential V λ0  and the temporarily stable voltage U* λy  forms a to-be-compared voltage U λZ ; the to-be-compared voltage U λZ  is connected to non-inverting terminals of the comparators C λ(Q−1) ˜C λ1 , and compared with the potential reference points V λ(Q−1) ˜V λ0 , so as to generate the stage-potential V λG ; through V λ(G+1) >U λZ >V λG , a threshold point G of comparison values I λ(Q−1) ˜I λ1  at stage λ satisfying requirements of I λ(Q−1) ˜I λ(G+1) =0 and I λG ˜I λ1 =1 is determined; let I λQ  constantly 0 and I λ0  constantly 1, the comparison values I λ(Q−1) ˜I λ0  are encoded by an encoder BM λ , and then digital output values D λ(q−1) ˜D λ0  of the stage-potential V λG  are obtained; herein, with the stage-potential V λG  as a bridge, the to-be-compared U λZ  is converted into the stage-potential V λG  and further into the digital signals D λ(q−1) ˜D λ0 ; 
 (2) a switch error reducing module which reduces switch errors by applying identical elevation to the potential of the reference points and the input voltage, or through a lossless switch; 
 (3) a stage-potential V λG  extracting module, wherein all sub-stages in AD## needs to extract out the stage-potential V λG  for a preparation of the conversion at next sub-stage, except the final sub-stage; the stage-potential is extracted for the conversion at next sub-stage; given that a conversion bit number of each sub-stage is q, Q=2 q , the voltage V p  is divided by the resistor chain into Q equal voltages ΔV; each ΔV is a fixed value ΔV=V p /Q; the reference potential points V λ(Q−1) ˜V λ0  are arithmetically connected to the switch points S λ(Q−1) ˜S λ0  one by one; a strobe point S λG  is determined through a strobe control of the threshold switch group; the strobe point S λG  corresponds to the stage-potential V λG , and sends the stage-potential V λG  into a switch main line S λ ; 
 (4) an inter-stage operation module, comprising a sampler/holder CB λ , a residue summator Σ λ  and a residue amplifier FD λ , wherein the input voltage U λy  at stage λ becomes the stable U* λy  through the sampler/holder CB λ , in such a manner that the m sub-stages are able to run parallel; the residue summator Σ λ  generates a residue voltage U λX =U λZ −V′ λG −V λS ; the residue voltage U λx  is within 0˜ΔV; the residue amplifier FD λ  amplifies a residue voltage signal Q times, so as to generate U (λ+1)y =U μy =Q*U λx ; as a result, a range of U μy  expands into a full scale of 0˜V p , and U μy  becomes the input voltage at stage μ; the input voltage U μy  at stage μ enters AD# μ  at stage μ for measurement and conversion at a higher accuracy; and 
 (5) a logarithmic conversion module and a process thereof comprising an analog conversion and a digital conversion, wherein the digital conversion is based on converting an overall input voltage Uαy into high-bit digital signals having equal quantization distances, and then converting the high-bit digital signals into low-bit digital signals having logarithmic quantization distances through a logarithm table; the analog conversion is based on converting a linear input voltage into the logarithmic input voltage through an analog logarithm converter before inputting into stage α, while actually ADC is for converting the logarithmic input voltage into the digital signals having the logarithmic quantization distances. 
 
     
     
       5. The multi-stage parallel super-high-speed ADC and DAC of the logarithmic companding law, as recited in  claim 1 , wherein an m stages*q-bit equal resistance logarithmic DAC is established as follows, wherein N-bit digital signals are allocated as m stages*q-bit: (D (N−1) ), . . . , D 0 )=(D α(q−1) , . . . , D α0 ), (D β(q−1) , . . . , D β0 ), . . . , (D m(q−1) , . . . , D m0 ); D are sent into control terminals of correspondent stage-potential switches: (d α(q−1) , . . . , d α0 ), (d β(q−1) , . . . , d β0 ), . . . , (d m(q−1) , . . . , d m0 ); the sub-DAC λ  at stage λ processes the digital signals at stage λ (D λ(q−1) , . . . , D λ0 ) with a DA conversion through following four modules and processes thereof:
 (1) a stage-potential V λG  generating module, wherein Q=2 q ; a voltage-dividing resistor chain R λQ ˜R λ0  of a parallelizer at stage λ forms potential reference points V λ(Q−1) ˜V λ0  at stage λ; after the stage-potential V λG  generating module receives the digital signals (D λ(q−1) , . . . , D λ0 ), the reference potential point V λG  correspondent to the digital signals becomes a stage-potential; V λ0  is a bottom potential; 
 (2) a switch error reducing module, identical to the switch error reducing module of Embodiment 2.1; 
 (3) a stage-potential V λG  extracting module, wherein the stage-potential V λG  of each stage needs to be extracted out for calculating an output voltage V λΨ  of each stage; the stage-potential V λG  extracting module and a process thereof are identical to the stage-potential V λG  extracting module and process in Embodiment 2.1; 
 (4) an inter-stage operational module, wherein the stage-potential V λG , the output voltage V λΨ  and an attenuation coefficient Ψ λ  have a relation of: V λΨ =V λG /Ψ λ , wherein Ψ λ =Q (λ−1) , namely an attenuation coefficient of an attenuator Ψ λ  at stage λ is Ψ λ =Q (λ−1) ; a summation of V λΨ  of all stages is executed by an overall summator Σ Ψ , so as to generate an overall output analog voltage V Ψ ; through the attenuator and the overall summator, the bottom potential of each stage becomes equal to a constant V RS : V RS =V α0 /Ψ α +V β0 /Ψ β + . . . +V m0 /Ψ m =V α0 /(Q m−α )+V β0 /(Q m−β )+ . . . +V m0 /(Q m−m ); a waveform of the overall output analog voltage V Ψ  is only elevated by V RS , without being transformed; the waveform of the overall output analog voltage V Ψ  is obtained by subtracting V RS  in the overall summator Σ Ψ ; and 
 (5) a logarithmic conversion module comprising an analog conversion module and a digital conversion module, wherein the digital conversion module is based on, after receiving low-bit digital signals having logarithmic quantization distances, converting the digital signals into high-bit digital signals having equal quantization distances through an anti-logarithm table, and then converting the high-bit digital signals into analog signals by a high-bit DAC having equal quantization distances; the analog conversion module is based on, after accomplishing the DA conversion by the DAC, converting the logarithmic analog signals into a linear output voltage by an analog anti-logarithmic converter. 
 
     
     
       6. The multi-stage parallel super-high-speed ADC and DAC of the logarithmic companding law, as recited in  claim 1 , wherein a two-stage logarithmic chain ADC is establish as follows; the logarithmic chain ADC comprises two sub-stages, LAD# α  and LAD# β ; LAD# α  is a first-stage logarithmic chain sub-ADC, and LAD# β  is a second-stage logarithmic chain sub-ADC; the two-stage logarithmic chain ADC further comprises a lossless switch; wherein
 the first-stage LAD# α  executes a q-bit conversion; a logarithm law resistor chain R Q ˜R 1  and R θ  divides a voltage 0˜V P  into Q+1 segments, forming Q+2 potential points; except 0 and V P , V Q−1 ˜V θ  are reference potential points, or quantized points, which have Q=2 q  steps; the reference potential chain V Q−1 ˜V θ  are set based on the logarithm law; V Q−1 ˜V 1  are connected to inverting terminals of correspondent first-stage comparators C Q−1 ˜C 1 , and a first-stage to-be-compared voltage U αZ  is connected to non-inverting terminals of each first-stage comparator, so as to generate first-stage comparison values I Q−1 ˜I 1 ; through encoding the first-stage comparison values by a first-stage encoder BM, first-stage logarithmic digital output signals D q−1 ˜D 0  are generated; a stage-potential V G  of the to-be-compared voltage U αZ  is obtained by controlling a stage-potential switch JDWKG via the first-stage comparison values I Q−1 ˜I 1  or the digital output signals D q−1 ˜D 0 , namely obtaining a rough result of U αZ  about a detection that to which segments of the first-stage-potential chains the to-be-compared voltage U αZ  belongs; the to-be-compared voltage U αZ  is connected to first-stage summators Σ Q−1 ˜Σ 0  to be a minuend, and the reference potential points V Q−1 ˜V θ  are correspondently connected to Σ Q−1 ˜Σ 0  to be subtrahends, so as to generated difference voltages U X(Q−1) ˜U X0 ; then, the difference voltages U X(Q−1) ˜U X0  are sent into first-stage amplifiers F Q−1 ˜F 0  to generate operational voltages U y(Q−1) ˜U y0 ; the difference voltage correspondent to the stage-potential V G  is called a residue voltage U XG ; the operational voltage correspondent to the stage-potential V G  is called an operational stage-potential U yG ; the summators acquires that the residue voltage U XG =U αZ −V G  and that U XG  ranges within (0˜ΔV G ), wherein ΔV G  is a quantization distance of the stage-potential; ΔV G =(V (G+1) −V G ); let an amplification coefficient of the amplifier F G  be V p /ΔV G , the amplifier F G  generates the operational stage voltage U yG =U XG *V p /ΔV G ; after U XG  is amplified into U yG , the voltage range expands into a full scale of 0˜V p ; the stage-potential switch extracts out the operational stage voltage U yG  and sends the extracted U yG  into a switch main line S α  towards the next stage; U yG  becomes the to-be-compared voltage at the next stage U βZ  after being sampled and held by a sampler/holder CB β , before an accurate measurement at the next stage; the input voltages of the two sub-stages maintain independent and stable within a sampling cycle due to the inter-stage sampler/holder CB β , in such a manner that the two sub-stages are capable of parallel operating and forming a pipeline type conversion; 
 the second-stage LAD# β  mainly comprises a second-stage logarithmic chain parallelizer LBXQ β , wherein second-stage logarithmic resistor chain R′ T ˜R′ 1  form potential points V P  and V′ T−1 ˜V′ 0 ; except V p , V′ T−1 ˜V′ 0  are second-stage logarithmic reference potential points; V′ T−1 ˜V′ 1  are connected to correspondent inverting terminals of second-stage comparators C′ T−1 ˜C′ 1 , and the second-stage to-be-compared voltage U βZ  is connected to a non-inverting terminal of each second-stage comparator, so as to generate second-stage comparison values I′ T−1 ˜I′ 1 ; then the second-stage comparison values I′ T−1 ˜I′ 1  are encoded by a second-stage encoder BM′ to generate second-stage logarithm law digital signals D′ t−1 ˜D′ 0 ; the two sub-stages, LAD# α  and LAD# β , together accomplish the digital signals conversion of the q+t bits logarithm law, wherein D q−1 ˜D 0  are high bit and D′ t−1 ˜D′ 0  are low bit; 
 the logarithmic resistor chain is for increasing an SNR and broadening a signal dynamic range; the resistor chains of the two sub-stages, LAD# α  and LAD# β  are set according to the logarithm law as follows; 
 the first-stage resistor chain is logarithmically provided, wherein the resistor chain of LAD# α  has a constant resistance, so a chain current I α  is also constant; let a base potential V θ  be equal to a minimum effective detection value of a sensor, and let a base resistance R θ =V θ /I α  and R A /R θ =η−1, wherein R A  is a virtual start resistance, the first-stage chain resistances successively increase by a large ratio of η T  from R A , which forms a large ratio resistor chain: R 1 =R A *η T , R 2 =R A *η 2 * T , . . . , R Q−3 =R A *η (Q−3) * T , R Q−2 =R A *η (Q−2) * T , R Q−1 =R A *η (Q−1) * T ; the large ratio resistor chain R θ ˜R Q  forms a large ratio potential chain (V j+1 /V j =η T ): ground, V η , V 1 =V θ *η T , V 2 =V θ *η 2 * T , V 3 =V θ *η 3 * T , . . . , V Q−2 =V θ *η (Q−2) * T , V Q−1 =V θ *η (Q−1) * T , V Q =V θ *η Q * T =V p ; except point V Q =V P , totally Q reference potential points, also called quantized points, are: V θ , V 1 , . . . , V Q−1 ; because a region below V θ  is an invalid detection region of the sensor, V θ  is the quantized point of the region of (V 1 ˜V θ ˜0) which is marked as (V 1 ˜V θ ˜0)→V θ ; quantization intervals of the other quantized points are: (V 2 ˜V 1 ]→V 1 , (V 3 ˜V 2 ]→V 2 , . . . , (V Q−1 ˜V Q−2 ]→V Q−2 , (V Q ˜V Q−1 ]→V Q−1 ; since the first-stage quantized points are rough because of the large ratio η T , it is necessary to insert T second-stage fine quantized points having a small ratio of 71 therebetween; 
 the second-stage resistor chain is logarithmically provided; the resistor chain of LAD# β  comprises T=2 t  resistors R′ 1 ˜R′ T ; at the first stage, the residue voltage U XG =U αZ −V G  ranges within (0˜ΔV G ); ΔV G =(V (G+1) −V G ); V G =V θ *η G * T , V (G+1) =V θ *η (G+1) * T , wherein ΔV G  is the quantization step of the first-stage stage-potential V G ; theoretically, T fine quantized points of the second sub-stage need to be inserted into V G ˜V (G+1) ; the fine quantized points of V G ˜V (G+1)  comprise V″ 0 =V G =V θ *η G * T , V″ 1 =V G *η 1 , V″ 2 =V G *η 2 , V″ 3 =V G *η 3 , . . . , V″ T−2 =V G *η T−2 , V″ T−1 =V G *η T−1 , wherein the fine quantized points increase geometrically by a ratio of η; thus, once the second-stage resistor chain has the geometrical relation of η and is multiplied by a coefficient, the second-stage resistor chain is capable of accomplishing the logarithmic conversion of the residue voltage; actually, the second-stage conversion is extracting out the first-stage residue voltage U XG , rather than inserting the fine quantized points into V G ˜V (G+1) ; U XG  ranges within (0˜ΔV G ); the first-stage residue voltage U XG  expands into the first-stage operational stage voltage U yG  after being amplified by the correspondent amplifier F G ; let the amplification coefficient of the amplifier F G  be V P /ΔV G , U yG =U XG *V P /ΔV G , and the range of (0˜ΔV G ) is expanded into a second-stage full scale of 0˜V p ; the operational stage-potential U yG  becomes the second-stage to-be-compared voltage U βZ  after being sampled and held by the sampler/holder CB β ; it is a key of the second-stage resistor chain to establish the logarithm law quantized points; in the second-stage resistor chain, given that R B  is an arbitrary virtual resistance, values of T chain resistors increase geometrically by the ratio of η: R′ 1 =R B *η 1 , R′ 2 =R B *η 2 , R′ 3 =R B *η 3 , . . . , R′ T−2 =R B *η T−2 , R′ T−1 =R B *η T−1 , R′ T =R B *η T , and then naturally T quantized points whose potentials geometrically increase by the ratio of η are formed: 0, V′ 1 =V B *η 1 , V′ 2 =V B *η 2 , V′ 3 =V B *η 3 , . . . , V′ T−2 =V B *η (T−2) , V′ T−1 =V B *η (T−1) , as well as the quantization intervals thereof: (V′ 1 ˜0]→0, (V′ 2 ˜V′ 1 ]→V′ 1 , (V′ 3 ˜V′ 2 ]→V′ 2 , . . . , (V′ T−1 ˜V′ T−2 ]→V′ T−2 , (V′ T ˜V′ T−1 ]→V′ T−1 ; V′T=V P  is excluded from the second-stage quantized points; and 
 herein, the logarithmic ADC with two resistor chains of the two sub-stages convert the analog signals into the logarithmic digital signals having a constant SNR; further, if the base resistance R θ  is adjusted into an adjustment resistance R* θ , wherein R* θ =R θ ˜R θ /15, let R* θ  be the minimal effective signal of the sensor, by reducing the adjustment resistance R* θ , the SNR curve decreases at a small signal terminal, and the dynamic range expands. 
 
     
     
       7. The multi-stage parallel super-high-speed ADC and DAC of the logarithmic companding law, as recited in  claim 1 , wherein a two-stage logarithmic chain DAC is establish as follows; the two-stage logarithmic chain DAC comprises a resistor chain and a reference potential chain which are in a logarithmic relation; the DAC receives logarithm law digital signals comprising high bit D q−1 ˜D 0 , and low bit D′ t−1 ˜D′ 0 , wherein the high bit D q−1 ˜D 0  are correspondently sent into control terminals d q−1 ˜d 0  of a first-stage multi-channel switch, so as to generate a first-stage stage-potential V G ; and the low bit D′ t−1 ˜D′ 0  are correspondently sent into control terminals d′ t−1 ˜d′ 0  of a second-stage multi-channel switch, so as to generate a second-stage stage-potential V′ B ; let b equal to some point within (0˜T−1), V′ b  is called a reference potential point at second-stage step b, wherein a strobe potential point is the second-stage stage-potential V′ B ; the two-stage logarithmic chain DAC further comprises a lossless switch;
 LDA# β  comprises DZL β , JDWKG′ and Σ βU ; DZL β , a second-stage logarithmic resistor chain, comprises a second-stage logarithmic resistor chain R′ T ˜R′ 1 , and second-stage logarithmic reference potential points V′ T−1 ˜V′ 0 ; the second-stage resistor chain is logarithmically provided as illustrated in Embodiment 4.1 of the present invention; 
 the second-stage resistor chain forms the T reference potential points V′ T−1 ; V′ T−2 , . . . , V′ 1 , V′ 0 , and quantization intervals thereof (V′ 1 ˜0]→>V′ 0 , (V′ 2 ˜V′ 1 ]→V′ 1 , (V′ 3 ˜V′ 2 ]→V′ 2 , . . . , (V′ T−1 ˜V′ T−2 ]→V′ T−2 , (V′ T ˜V′ T−1 ]→V′ T−1 ; a quantization step, or a step difference, of V′ b  is ΔV′ b =V′ b+1 −V′ b ; after the control terminals d′ t−1 ˜d′ 0  of the second-stage stage-potential switch JDWKG′ receive the low bit digital signals D′ t−1 ˜D′ 0 , a strobe point S′ b  is determined among second-stage switch points S′ T−1 ˜S′ 0  and specially marked as S′ B ; the potential point V′ b  correspondent to the strobe point S′ B  is a second-stage stage-potential V βB ; the second-stage stage-potential V βB  ranges within the T potential points V′ 0 , V′ 1 , . . . , V′ T−2 , V′ T−1  whose quantization intervals respectively are: (V′ 1 ˜V′ 0 ]→V′ 0 , (V′ 2 ˜V′ 1 ]→V′ 1 , (V′ 3 ˜V′ 2 ]→V′ 2 , . . . , (V′ T−1 ˜V′ T−2 ]→V′ T−2 , (V′ T ˜V′ T−1 ]→V′ T−1 , so an analog voltage correspondent to the second-stage stage-potential V βB  ranges within 0˜V P ; 
 LDA# α  comprises DZL α , SJQH, JDWKG, and Σ AU ; DZL α , a first-stage logarithmic resistor chain, comprises a first-stage logarithmic resistor chain R Q ˜R 1  and R θ , and first-stage logarithmic reference potential points V Q−1 ˜V θ ; the first-stage resistor chain is logarithmically provided; let g be an arbitrary one of 0˜(Q−1), each first-stage-potential point V g  is correspondently connected to an summator Σ g , an attenuator Ψ g  and a switch point S g , so as to form a branch g; the voltage between the potential point V g  and the potential point V g+1  is called a step difference ΔV g  of the potential point V g , wherein ΔV g =V g+1 −V g ; 
 the second-stage stage-potential V βB  is summed with the first-stage stage-potential V G  as the residue voltage of the stage-potential V G ; the range 0˜V P  of V βB  is attenuated into 0˜ΔV g  through the attenuator Ψ g ; because ΔV g  at each step is unequal but geometric, an attenuation coefficient ψ g  of the attenuator Ψ g  at each step is also geometric; let ψ g =ΔV g /V P , the second-stage stage-potential V βB  is changed into an attenuated value V Ψg  based on an attenuation calculation of V Ψg =V βB *ψ g =V βB *ΔV g /V P , in such a manner that the range 0˜V P  of V βB  is attenuated into the range 0˜ΔV g  of V Ψg ; the attenuated voltage V Ψg  is the residue voltage at step g of the first-stage reference potential points V Q−1 ˜V θ  before becoming the strobe potential; the first-stage reference potential V g  is a rough analog value, while the correspondent attenuated voltage V Ψg  as the residue voltage of V g  is a fine analog value; V g  is summed with V Ψg  through the summator Σ g , so as to generate a sum of the first-stage rough analog value V g  and the second-stage fine analog value V Ψg ; the sum thereof is called a reference potential sum value V Σg ; each first-stage reference potential V g  has a correspondent reference potential sum value V Σg  to be outputted; after the control terminals d q−1 ˜d 0  of the first-stage stage-potential switch JDWKG receive the high bit digital signals D q−1 ˜D 0 , a first-stage strobe point S G  is determined, and then the reference potential sum value V Σg  correspondent to the first-stage strobe point is outputted as a stage-potential sum value U ΣG  into a collector Σ αU ; actually, the collector Σ αU  only receives the single stage-potential sum value U ΣG  which is outputted in a form of a DA conversion value U αβ ; herein, the two-stage logarithmic chain DAC finishes the conversion. 
 
     
     
       8. The multi-stage parallel super-high-speed ADC and DAC of the logarithmic companding law, as recited in  claim 1 , wherein a two-stage logarithmic chain DAC having half-step quantization points is established, and reference potential points of the DAC are the half-step quantization points; half-step reference points are formed by moving all of the reference potential points a half step up; half-step resistances are formed by moving all of the resistances the half step up; U g  represents a first-stage half-step reference point; P g  represents a first-stage half-step resistance; U′ b  represents a second-stage half-step reference point; P′ b  represents a second-stage half-step resistance; a correspondence between a resistor chain of the DAC having the half-step quantization points and the resistor chain of the DAC is U g →V g , P g →R g , U′ b →V′ b , P′ b →*R′ b ; the half-step means moving the original reference potential points the half step up, calculated as: moving all the reference potential points the half step up generates the first-stage half-step reference point U g =(V g +V g *η)/2, the first-stage half-step resistance P g =(R g +R g *η)/2, the second-stage half-step reference points U′ b =(V b +V b *η)/2, and the second-stage half-step resistance P′ b =(R′ b +R′ b *η)/2, so as to accomplish moving all of the reference potential points and the resistance the half step up. 
     
     
       9. The multi-stage parallel super-high-speed ADC and DAC of the logarithmic companding law, as recited in  claim 1 , wherein a digital logarithmic converter is established, wherein a linear analog signal is firstly converted into an N-bit logarithm law digital signal by the two-stage N-bit logarithmic chain ADC, and then converted into an output analog signal by a N-bit linear DAC; and the output analog signal is an analog signal based on a logarithm law. 
     
     
       10. The multi-stage parallel super-high-speed ADC and DAC of the logarithmic companding law, as recited in  claim 1 , wherein a digital anti-logarithmic converter is established, wherein an analog signal based on a logarithm law is firstly converted into an N-bit logarithm law digital signal by an N-bit linear ADC, and then converted into an output analog signal by an N-bit two-stage logarithmic chain DAC; and the output analog signal is a linear analog signal.