Directed per bank refresh command

Abstract

A memory device includes a per bank refresh counter applicable to multiple banks in a group. The memory device increments a row address counter only when the per bank refresh counter is reset. The memory device receives a per bank refresh command from an associated memory controller, and performs a per bank refresh in response to receiving the per bank refresh command. The memory device refreshes a row identified by a row address counter for a bank identified by the per bank refresh command. The memory device increments the per bank refresh counter in response to receiving the per bank refresh command, and increments the row address counter when the per bank refresh counter is reset, either by rolling over or by a reset condition.

What is claimed is: 
     
       1. A method comprising:
 receiving a per bank refresh command at a memory device from a memory controller that specifies an order at which banks are to be refreshed; 
 performing a per bank refresh in response to receiving the per bank refresh command for a bank identified by the command at a row identified by a row address counter, the bank being identified consistent with the order; 
 incrementing a per bank refresh counter in response to receiving the per bank refresh command; 
 determining if incrementing the per bank refresh counter causes the per bank refresh counter to roll over; and 
 when the per bank refresh counter rolls over, incrementing the row address counter; 
 otherwise, maintaining the row address counter at a current value for a subsequent per bank refresh command. 
 
     
     
       2. The method of  claim 1 , wherein receiving the per bank refresh command comprises receiving a command to refresh a bank out of bank address order. 
     
     
       3. The method of  claim 2 , wherein receiving the command out of bank address order comprises receiving the command to refresh the banks in a random order. 
     
     
       4. The method of  claim 1 , wherein performing the per bank refresh comprises refreshing all banks via per bank refresh command prior to repeating a per bank refresh of any of the banks. 
     
     
       5. The method of  claim 1 , wherein incrementing the per bank refresh counter comprises incrementing a counter applicable to all banks in a channel. 
     
     
       6. The method of  claim 1 , wherein incrementing the per bank refresh counter comprises incrementing a counter applicable to multiple banks, for a subset of banks in a channel. 
     
     
       7. The method of  claim 1 , further comprising:
 clearing the per bank refresh counter in response to detecting a reset condition. 
 
     
     
       8. The method of  claim 7 , wherein the reset condition comprises a memory subsystem reset signal generated in response to a power-up condition. 
     
     
       9. The method of  claim 7 , wherein the reset condition comprises exit of the memory device from self-refresh. 
     
     
       10. The method of  claim 7 , wherein the reset condition comprises receiving an all bank refresh command from the memory controller. 
     
     
       11. A memory device comprising:
 multiple banks of memory, each having multiple rows; 
 connectors to couple to a memory controller and receive a per bank refresh command from the memory controller, the per bank refresh command to also identify a specific one of the multiple banks to refresh, the connectors to also receive a bank refresh order from the memory controller; 
 a row address counter to indicate a row address to refresh for the specific bank identified by the per bank refresh command; 
 a per bank refresh counter to increment in response to receiving the per bank refresh 
 logic to determine if incrementing the per bank refresh counter causes the per bank refresh counter to roll over, and when the per bank refresh counter rolls over, to increment the row address counter; otherwise, to maintain the row address counter at a current value for a subsequent per bank refresh command. 
 
     
     
       12. The memory device of  claim 11 , wherein the banks of memory are grouped as separate subsets, and wherein the per bank refresh counter is applicable to all banks in a subset, but not to banks of other subsets. 
     
     
       13. The memory device of  claim 11 , the logic to further clear the per bank refresh counter in response to detecting a reset condition. 
     
     
       14. The memory device of  claim 13 , wherein the reset condition comprises one of a memory subsystem reset signal generated in response to a power-up condition, exit of the memory device from self-refresh, or receiving an all bank refresh command from the memory controller. 
     
     
       15. A memory subsystem comprising:
 connectors to couple to a memory device having multiple rows of memory; 
 a memory controller device coupled to the connectors, the memory controller device to
 determine to issue a per bank refresh to refresh a specific one of multiple memory banks instead of an all bank refresh; 
 determine a per bank ordering pattern for the multiple memory banks; 
 transmit a per bank refresh command to the memory device to cause the memory device to perform a per bank refresh for a bank identified by the refresh command at a row identified by a row address counter, wherein the memory device increments a per bank refresh counter in response to the refresh command, and increments a row address counter only in response to a per bank refresh counter reset condition, and otherwise, maintains the row address counter at a current value for a subsequent per bank refresh command. 
 
 
     
     
       16. The memory subsystem of  claim 15 , wherein the order pattern comprises an order out of bank address order. 
     
     
       17. The memory subsystem of  claim 16 , wherein the out of bank address order pattern comprises a different order for each cycle of per bank refresh commands. 
     
     
       18. The memory subsystem of  claim 15 , wherein the memory controller device to determine to issue the per bank refresh further comprises the memory controller to refresh all banks via the per bank refresh command prior to repeating a per bank refresh of any of the banks. 
     
     
       19. The memory subsystem of  claim 15 , wherein the reset condition comprises one of a rolling over of the per bank refresh counter, a memory subsystem reset signal generated in response to a power-up condition, exit of the memory device from self-refresh, or receiving an all bank refresh command from the memory controller device. 
     
     
       20. An electronic device comprising:
 a hardware platform including a processor; 
 a memory device on the hardware platform to receive communication from a memory controller device on the hardware platform, the memory device including
 multiple banks of memory, each having multiple rows; 
 connectors to couple to a memory controller and receive a per bank refresh command from the memory controller, the per bank refresh command to identify a specific one of the multiple banks to refresh, the connectors to also receive a bank refresh order from the memory controller; 
 a row address counter to indicate a row address to refresh for the specific bank identified by the per bank refresh command; 
 a per bank refresh counter to increment in response to receiving the per bank refresh command; and 
 logic to determine if incrementing the per bank refresh counter causes the per bank refresh counter to roll over, and when the per bank refresh counter rolls over, to increment the row address counter; otherwise, to maintain the row address counter at a current value for a subsequent per bank refresh command; and 
 
 a touchscreen display coupled to generate a display based on data accessed from the memory device. 
 
     
     
       21. The electronic device of  claim 20 , the memory device further including multiple access channels, wherein each channel provides access to specific banks of memory, wherein the per bank refresh counter is applicable to all banks in a channel, but not to banks of other channels. 
     
     
       22. The electronic device of  claim 20 , the memory device logic to further clear the per bank refresh counter in response to detecting a reset condition, including one of a memory subsystem reset signal generated in response to a power-up condition, exit of the memory device from self-refresh, or receiving an all bank refresh command from the memory controller.