Power-efficient sensory recognition processor

Abstract

This invention provides a computer and/or processor architecture optimized for power-efficient computation of a class of sensory recognition (e.g. vision) algorithms on a single computer chip derived from research into how humans process sensory information, such as vision. The processor for efficiently recognizing sensory information with recognizable features defines a feature recognition engine that resolves features from the sensory information and provides a feature information input. A plurality of processing nodes, arranged in a hierarchy of layers, receives the input and, in parallel, recognizes multiple components of the features. Recognized features are transferred between the layers so as to build likely recognition candidates and remove unlikely recognition candidates. A memory in each of the nodes refreshes and retains predetermined features related to likely recognition candidates as the features are transferred between the layers. A thresholding process determines when at least one of the recognition candidates sufficiently matches predetermined criteria.

What is claimed is: 
     
       1. A processor for efficiently recognizing sensory information including a plurality of recognizable features comprising:
 a feature recognition engine that resolves features from the sensory information and provides a feature information input; and 
 a plurality of processing nodes, arranged in a hierarchy of layers, receiving the input at a lowest layer thereof and being constructed and arranged to simultaneously, and in parallel recognize multiple components of the features, so as to build likely recognition candidates and remove unlikely recognition candidates, wherein 
 communication from one layer to a next-higher layer is through an ascending communication bus, and from one layer to a next-lower layer is through a descending communication bus, 
 wherein the communications are transferred efficiently such that a node sends a communication by inserting a message into an outbound buffer, and wherein a selector chooses which buffer is permitted to communicate over the bus, and wherein sub-features arriving at a node over the inbound ascending bus may cause communication on both the outbound ascending and outbound descending bus, and 
 wherein features arriving at a node over the inbound descending bus may cause communication only on the outbound descending bus. 
 
     
     
       2. The processor as set forth in  claim 1  further comprising a memory in each of the nodes that is constructed and arranged to refresh and retain predetermined features related to likely recognition candidates as the features are transferred between the layers. 
     
     
       3. The processor as set forth in  claim 2  further comprising a thresholding process in each of the nodes that determines when at least one of the recognition candidates sufficiently matches predetermined criteria. 
     
     
       4. The processor as set forth in  claim 3  further comprising an overseer that is provided with the recognition candidates that sufficiently match the predetermined criteria, and in response thereto, directs a function to occur. 
     
     
       5. The processor as set forth in  claim 1  wherein the sensory information is visual information and the feature recognition engine receives image data from at least one image sensor. 
     
     
       6. The processor as set forth in  claim 1  further comprising a DRAM for storing feature data, and wherein the DRAM does not refresh the feature data that is to be erased. 
     
     
       7. The processor as set forth in  claim 1  further comprising a first memory at each node from which features are retrieved using a hash table data structure, and a second memory that is constructed and arranged to retain high-level feature structures,
 wherein at least one of the features is stored in the hash table at a position indicated by a hash key calculated from the location and scale of the one of the features, and 
 wherein features are retrieved from the hash table if they are present at keys output by a unit calculating the locations and scales of features related to an input feature as determined by high-level feature structures held within the second memory, and 
 wherein successful retrieval of features from the hash table defines a criterion indicating an object recognition candidate. 
 
     
     
       8. The processor as set forth in  claim 1  further comprising a match quality filtering unit receiving a closest matching feature of the features as input and filtering matches further so that a minimum match quality is maintained by the outputs of the unit, and wherein the outputs of the match quality filtering unit are defined as recognition candidates.