Adaptive on die decoupling devices and methods

Abstract

Semiconductor dies and methods are described, such as those including a first capacitive pathway having a first effective series resistance (ESR) and a second capacitive pathway having an adjustable ESR. One such device provides for optimizing the semiconductor die for different operating conditions such as operating frequency. As a result, semiconductor dies can be manufactured in a single configuration for several different operating frequencies, and each die can be tuned to reduce (e.g. minimize) supply noise, such as by varying the ESR or the capacitance of at least one of the pathways.

What is claimed is: 
     
       1. An electronic system, comprising:
 a semiconductor memory connected to a processor; 
 a connection between power and the semiconductor memory, including:
 a first capacitive pathway, comprising a first effective series resistance, between a first power supply and a second power supply, the first capacitive pathway being located on a semiconductor die; 
 a second capacitive pathway, comprising a second effective series resistance, the second capacitive pathway coupled in parallel with the first capacitive pathway between the first power supply and the second power supply, wherein the second effective series resistance is adjustable. 
 
 
     
     
       2. The electronic system of  claim 1 , wherein a capacitance of the second capacitive pathway is adjustable. 
     
     
       3. The electronic system of  claim 1 , further comprising a third capacitive pathway, the third capacitive pathway comprising a third effective series resistance, the third capacitive pathway coupled in parallel with the first and second capacitive pathways between the first power supply and the second power supply, and wherein the third effective resistance is adjustable. 
     
     
       4. The electronic system of  claim 1 , further comprising a control circuit, configured to adjust the second effective series resistance to select a desired amount of supply noise for a given operating frequency. 
     
     
       5. The electronic system of  claim 1 , further comprising a control circuit, configured to adjust the second effective series resistance to select a desired amount of supply noise for a given operating frequency. 
     
     
       6. The electronic system of  claim 5 , further comprising a noise sensor, wherein the noise sensor and the control circuit are configured to determine a desired effective series resistance value that corresponds to the desired amount of supply noise. 
     
     
       7. An electronic system, comprising:
 a semiconductor memory connected to a processor; 
 a connection between power and the semiconductor memory, including:
 a first capacitive pathway, comprising a first effective series resistance, between a first power supply and a second power supply, the first capacitive pathway being located on a semiconductor die; 
 a metal-oxide-semiconductor (MOSCAP) based capacitive pathway, comprising a second effective series resistance, the second capacitive pathway coupled in parallel with the first capacitive pathway between the first power supply and the second power supply, wherein the second effective series resistance is adjustable. 
 
 
     
     
       8. The electronic system of  claim 7 , wherein the second capacitive pathway provides a capacitance of approximately 50 pF. 
     
     
       9. The electronic system of  claim 8 , wherein the second effective series resistance is adjusted to approximately 11 ohms. 
     
     
       10. The electronic system of  claim 7 , wherein the second capacitive pathway provides a capacitance of approximately 400 pF. 
     
     
       11. The electronic system of  claim 10 , wherein the second effective series resistance is adjusted to approximately 11 ohms. 
     
     
       12. An electronic system, comprising:
 a semiconductor memory connected to a processor; 
 a connection between power and the semiconductor memory, including:
 a first capacitive pathway, comprising a first effective series resistance, between a first power supply and a second power supply, the first capacitive pathway being located on a semiconductor die; 
 a metal-insulator-metal (MIM) based capacitive pathway, comprising a second effective series resistance, the second capacitive pathway coupled in parallel with the first capacitive pathway between the first power supply and the second power supply, wherein the second effective series resistance is adjustable. 
 
 
     
     
       13. The electronic system of  claim 12 , further comprising a control circuit, configured to adjust the second effective series resistance to select a desired amount of supply noise for a given operating frequency. 
     
     
       14. The electronic system of  claim 12 , wherein the second capacitive pathway provides a capacitance of approximately 50 pF. 
     
     
       15. The electronic system of  claim 14 , wherein the second effective series resistance is adjusted to approximately 11 ohms. 
     
     
       16. The electronic system of  claim 12 , wherein the second capacitive pathway provides a capacitance of approximately 400 pF. 
     
     
       17. The electronic system of  claim 16 , wherein the second effective series resistance is adjusted to approximately 11 ohms.