Process for manufactuirng super-barrier rectifiers

Abstract

A process for manufacturing a semiconductor device, wherein a semiconductor layer is formed on a body of semiconductor material; a first mask is formed on the semiconductor layer; a first conductive region is implanted in the body using the first mask; a second mask is formed laterally and complementarily to the first mask, at least in a projection in a plane parallel to the surface of the body; a second conductive region is implanted in the body using the second mask, in an adjacent and complementary position to the first conductive region; spacers are formed on the sides of the second mask region, to form a third mask aligned to the second mask; and, using the third mask, portions of the semiconductor layer are removed to form a gate region.

The invention claimed is: 
     
       1. A process for manufacturing a semiconductor device, comprising:
 forming a semiconductor layer on a surface of a semiconductor body; 
 forming a first mask on the semiconductor layer; 
 forming a first conductive region in the body by introducing a first dopant species into the body using the first mask; 
 forming a second mask laterally and complementarily to the first mask, at least in a projection in a plane parallel to the surface of the body; 
 forming a second conductive region in the body by introducing a second dopant species into the body using the second mask, in an adjacent and complementary position to the first conductive region; 
 forming a third mask aligned to the second mask by forming spacers on sides of the second mask; and 
 forming a gate region by removing portions of the semiconductor layer using the third mask. 
 
     
     
       2. The process according to  claim 1  wherein:
 the first mask includes a window; 
 forming a complementary mask arranged offset and complementarily with respect to at least one portion of the first mask after introducing the first dopant species by at least partially filling the window with a filling material; the second mask at least partially including the complementary mask or being congruent with respect to the complementary mask; and 
 removing the first mask after at least partially filling the window. 
 
     
     
       3. The process according to  claim 2  wherein the first mask is a probe mask;
 the first conductive region is a probe region; the second mask is a channel mask; and the second conductive region is a channel region. 
 
     
     
       4. The process according to  claim 2  wherein the semiconductor device is an adjustable field-effect rectifier diode, the process comprising, after removing portions of the semiconductor layer, and using the third mask:
 forming a well region by introducing third dopant species into the body; 
 forming a source region by introducing fourth dopant species into the channel region in a tilted way; 
 forming a microtrench by removing a portion of the body; and 
 depositing a conductive contacting layer filling the microtrench and extending at least on one side of the gate region and in electrical contact with the gate region, the source region, and the well region. 
 
     
     
       5. The process according to  claim 4  wherein the body, the first conductive region, and the source region have a first conductivity type, and the well region and the second conductive region have a second conductivity type. 
     
     
       6. The process according to  claim 4  wherein the semiconductor layer is of polysilicon, and the conductive contacting layer is metal. 
     
     
       7. The process according to  claim 2 , further comprising forming a masking layer prior to providing the first mask, on the semiconductor layer; and wherein forming the second mask includes removing portions of the masking layer using the complementary mask. 
     
     
       8. The process according to  claim 7  wherein introducing first dopant species and filling the first window are performed prior to removing portions of the masking layer; the complementary mask extends over the masking layer, laterally with respect to the first mask; and introducing first dopant species includes implanting the first dopant species through the masking layer. 
     
     
       9. The process according to  claim 8 , further comprising removing the complementary mask prior to forming spacers. 
     
     
       10. The process according to  claim 8  wherein removing the complementary mask is carried out before or after introducing second dopant species. 
     
     
       11. The process according to  claim 8  wherein the first mask is of first-type photoresist, and the filling material is a second-type photoresist. 
     
     
       12. The process according to  claim 11  wherein the first-type photoresist is positive, and the filling material is negative photoresist and, prior to removing the first mask, the structure is photoexposed blank. 
     
     
       13. The process according to  claim 2  wherein providing a first mask includes forming, on the semiconductor layer, a masking layer and first mask regions, and removing portions of the masking layer not covered by the first mask regions; and forming a second mask includes removing the first mask regions, and, after at least partially filling the window with filling material, removing remaining portions of the masking layer. 
     
     
       14. A method, comprising:
 forming a plurality of probe regions in a substrate, the forming of the probe regions including:
 forming a first mask having openings over an insulating layer and a conductive layer; 
 implanting a dopant through the openings in the first mask; 
 
 forming a second mask by filling the openings of the first mask; 
 removing the first mask; 
 forming a third mask by removing portions of the insulating layer using the second mask; 
 forming a plurality of channel regions using the third mask, the plurality of probe regions and the plurality of channel regions being self-aligned. 
 
     
     
       15. The method of  claim 14  wherein forming the third mask includes forming a spacer adjacent to sidewalls of the insulating layer. 
     
     
       16. The method of  claim 15 , further comprising forming a plurality of gate regions by removing portions of the conductive layer with the third mask before forming the plurality of channel regions, the third mask having openings between the gate regions. 
     
     
       17. The method of  claim 16  wherein forming the plurality of channel regions includes implanting a dopant through the openings in the third mask. 
     
     
       18. The method of  claim 17 , further comprising removing the third mask and forming a contact in the openings between the gate regions.