IC test circuitry with tri-state buffer, comparator, and scan cell

Abstract

A test controller applies test stimulus signals to the input pads of plural die on a wafer in parallel. The test controller also applies encoded test response signals to the output pads of the plural die in parallel. The encoded test response signals are decoded on the die and compared to core test response signals produced from applying the test stimulus signals to core circuits on the die. The comparison produces pass/fail signals that are loaded in to scan cells of an IEEE 1149.1 scan path. The pass/fail signals then may be scanned out of the die to determine the results of the test.

What is claimed is: 
     
       1. An integrated circuit comprising:
 A. input pads and output pads; 
 B. core circuitry having inputs coupled to the input pads and outputs coupled to the output pads; 
 C. test circuitry coupled between a certain output of the core circuitry and a certain output pad, the test circuitry including:
 i. a tri-state buffer having an input connected to the certain output of the core circuitry, an output coupled to the certain output pad, and an enable input; 
 ii. comparator circuitry having a core input coupled to the certain output of the core circuitry, an encoded response input coupled to the certain output pad, an enable input coupled to the enable input of the tri-state buffer, and a compare output; and 
 iii. a scan cell having a pass/fail input coupled to the compare output, a serial scan input, a boundary scan input, a serial scan output, and a serial scan control input. 
 
 
     
     
       2. The integrated circuit of  claim 1  in which the comparator circuitry includes:
 i. a trinary gate having an input coupled to the encoded response input, a first output, and a second output; 
 ii. an OR gate having an input coupled to the core input, an input coupled to the first output, and an output; and 
 iii. an AND gate having an input coupled to the second output of the trinary gate, an input coupled to the output of the OR gate, and the compare output. 
 
     
     
       3. The integrated circuit of  claim 2  in which the enable input lead is coupled to the trinary gate, the OR gate and the AND gate. 
     
     
       4. The integrated circuit of  claim 1  in which the test circuitry includes a pass/fail latch having a compare input coupled to the compare output of the comparator circuitry, a test enable input coupled to the enable input, and having a pass/fail output coupled with the pass/fail input. 
     
     
       5. The integrated circuit of  claim 4  in which the pass/fail latch includes an AND gate having an input coupled to the compare input, an output, and a flip-flop having an input coupled to the output of the AND gate, and having the pass/fail output. 
     
     
       6. The integrated circuit of  claim 1  in which the scan cell includes a multiplexer having scan inputs coupled to the pass/fail input, the serial scan input, and the boundary scan input, a control input coupled with the scan control input, and an output, and the scan cell including a flip-flop having a data input connected to the output of the multiplexer, a control input connected with the scan control input, and an output coupled with the serial scan output.