Display with multilayer and embedded signal lines

Abstract

A display may have a thin-film-transistor layer with a substrate layer. A layer of dielectric may be formed on the substrate layer and may have an upper surface and a lower surface. The thin-film-transistor layer may include an array of display pixels. Data lines and gate lines may provide signals to the display pixels. Gate driver circuitry in an inactive peripheral portion of the display may include a gate driver circuit for each gate line. The gate driver circuits may include thin-film transistors that are formed on the upper surface of the layer of dielectric. Signal lines such as a gate low line, a gate routing line coupled between the gate driver circuits, and a common electrode line may be formed from two or more layers of metal to reduce their widths or may be embedded within the dielectric layer between the upper and lower surfaces under the thin-film transistors.

What is claimed is: 
     
       1. A display, comprising:
 upper and lower polarizers; and 
 a thin-film transistor layer between the upper and lower polarizers, wherein the thin-film transistor layer includes a substrate layer, a rectangular array of display pixels controlled by signals on gate lines and data lines, and thin-film-transistor gate driver circuitry that supplies signals to the gate lines, wherein the gate driver circuitry includes thin-film transistors, wherein the thin-film transistor layer includes a dielectric layer on the substrate layer, and wherein the thin-film-transistor layer includes a common electrode voltage line that is embedded within the dielectric layer and that runs under the thin-film transistors. 
 
     
     
       2. The display defined in  claim 1  wherein the dielectric includes a material selected from the group consisting of silicon oxide and silicon nitride. 
     
     
       3. The display defined in  claim 2  wherein the substrate layer comprises glass and wherein the common electrode voltage line comprises metal. 
     
     
       4. The display defined in  claim 1  wherein the thin-film-transistor layer further comprises a gate low metal line that is embedded within the dielectric layer and that runs under the thin-film transistors parallel to the common electrode voltage line. 
     
     
       5. The display defined in  claim 4  wherein the thin-film transistor gate driver circuitry includes a plurality of gate driver circuits each of which provides a gate signal to a respective one of the gate lines, wherein the thin-film transistors are included in the gate driver circuits, and wherein the thin-film transistor gate driver circuitry includes at least one gate routing line that conveys signals between the gate driver circuits, that is embedded within the dielectric layer, and that runs under the thin-film transistors. 
     
     
       6. The display defined in  claim 5  further comprising:
 a color filter layer interposed between the first and second polarizers; and 
 a layer of liquid crystal material interposed between the color filter layer and the thin-film-transistor layer. 
 
     
     
       7. The display defined in  claim 6  wherein the thin-film-transistor layer further comprises a gate low metal line that is embedded within the dielectric layer and wherein the gate low metal line runs under the thin-film transistors parallel to the common electrode voltage line. 
     
     
       8. The display defined in  claim 1  wherein the common electrode voltage line distributes an electrical signal to a common electrode that controls the display pixels. 
     
     
       9. A display, comprising:
 upper and lower polarizers; 
 a thin-film transistor layer between the upper and lower polarizers; 
 a color filter layer between the upper and lower polarizers; and 
 a layer of liquid crystal material between the thin-film transistor layer and the color filter layer, wherein the thin-film transistor layer includes a substrate layer, gate and data lines on the substrate layer, a rectangular array of display pixels on the substrate layer that are controlled by signals on the gate lines and data lines, and thin-film-transistor gate driver circuitry that supplies signals to the gate lines, wherein the gate driver circuitry includes thin-film transistors, wherein the thin-film transistor layer includes a dielectric layer on the substrate layer, wherein the dielectric layer has opposing upper and lower surfaces, wherein the lower surface of the dielectric layer lies on an upper surface of the substrate layer, and wherein the thin-film transistors are formed on the upper surface of the dielectric layer, and wherein the thin-film transistor layer comprises at least one metal line that is embedded within the dielectric layer between the upper and lower surfaces and that runs under the thin-film transistors on the upper surface. 
 
     
     
       10. The display defined in  claim 9  wherein the at least one metal line includes a common electrode line, a gate low line, and a gate routing line. 
     
     
       11. The display defined in  claim 10  wherein the gate routing line is interposed between the common electrode line and the gate low line. 
     
     
       12. The display defined in  claim 9  wherein the at least one metal line comprises aluminum. 
     
     
       13. The display defined in  claim 9  wherein the dielectric layer includes a material selected from the group consisting of silicon oxide and silicon nitride. 
     
     
       14. The display defined in  claim 9  wherein the substrate layer comprises glass. 
     
     
       15. The display defined in  claim 9  wherein the thin-film transistor gate driver circuitry includes a plurality of gate driver circuits each of which provides a gate signal to a respective one of the gate lines, wherein the thin-film transistors are included in the gate driver circuits, and wherein the at least one metal line includes a gate routing line that conveys signals between the gate driver circuits. 
     
     
       16. The display defined in  claim 9  further comprising at least one conductive via in the dielectric layer that electrically couples the thin-film-transistor gate driver circuitry on the upper surface of the dielectric layer to the at least one metal line that is embedded within the dielectric layer.