Variable capacitance device

Abstract

A variable capacitance device including: first and second transistors coupled in parallel between first and second nodes of the capacitive device, a control node of the first transistor being adapted to receive a control signal, and a control node of the second transistor being adapted to receive the inverse of the control signal, wherein the first and second transistors are formed in a same semiconductor well.

What is claimed is: 
     
       1. A variable capacitance device comprising:
 a semiconductor well; 
 a first node; 
 a second node; 
 a first transistor including a first control node, the first control node being configured to receive a control signal; and 
 a second transistor including a second control node, the second control node being configured to receive an inverse of the control signal, the first and second transistors being coupled in parallel between the first and second nodes and arranged in the semiconductor well. 
 
     
     
       2. The variable capacitance device of  claim 1  wherein at least one dimension of the first transistor is different from a corresponding dimension of the second transistor. 
     
     
       3. The variable capacitance device of  claim 2  wherein the first and second transistors are dimensioned such that a capacitance between the first and second nodes differs by 1 aF or less between high and low states of the control signal. 
     
     
       4. The variable capacitance device of  claim 1  wherein the first control node is a first gate electrode, the second control node is a second gate electrode, the first gate electrode having a width or length that is different from a width or length of the second gate electrode. 
     
     
       5. The variable capacitance device of  claim 4  wherein the width or length of the first gate electrode is between 1 and 10 percent greater than the width or length of the second gate electrode. 
     
     
       6. The variable capacitance device of  claim 1  wherein the first control node is a first gate node, the second control node is a second gate node, the variable capacitance device further including:
 a first resistor coupled to the first gate node, the first resistor being configured to receive the control signal; and 
 a second resistor coupled to the second gate node, the second resistor being configured to receive the inverse of the control signal. 
 
     
     
       7. The variable capacitance device of  claim 1 , further comprising a capacitor coupled in parallel with the first and second transistors. 
     
     
       8. The variable capacitance device of  claim 1  wherein the second node is coupled to a supply voltage. 
     
     
       9. The variable capacitance device of  claim 1  wherein the first and second transistors are both n-channel MOS transistors or p-channel MOS transistors. 
     
     
       10. The variable capacitance device of  claim 1  wherein the first control node is a first gate node, the second control node is a second gate node, the variable capacitance device including an inverter coupled between the first and second gate nodes. 
     
     
       11. The variable capacitance device of  claim 1  wherein the first control node is a gate of the first transistor, and the second control node is a gate of the second transistor. 
     
     
       12. An electronic device, comprising:
 a control block configured to generate a control signal; and 
 a variable capacitance device coupled to the control block, the variable capacitance device including:
 a semiconductor well; 
 a first node; 
 a second node; 
 a first transistor including a first control node, the first control node being configured to receive the control signal; and 
 a second transistor including a second control node, the second control node being configured to receive an inverse of the control signal, the first and second transistors being coupled in parallel between the first and second nodes and arranged in the semiconductor well. 
 
 
     
     
       13. The electronic device of  claim 12  wherein at least one dimension of the first transistor is different from the corresponding dimension of the second transistor, and a capacitance between the first and second nodes when the control signal is in a high state is higher or lower than a capacitance between the first and second nodes when the control signal is in a low state. 
     
     
       14. The electronic device of  claim 12  wherein the variable capacitance device further includes:
 an inverter coupled to the second control node, the inverter being configured to receive the control signal and generate the inverse of the control signal. 
 
     
     
       15. A digitally controlled oscillator, comprising:
 a variable capacitance device including:
 a semiconductor well; 
 a first node; 
 a second node; 
 a first transistor including a first control node, the first control node being configured to receive a control signal; and 
 a second transistor including a second control node, the second control node being configured to receive an inverse of the control signal, the first and second transistors being coupled in parallel between the first and second nodes and arranged in the semiconductor well; and 
 
 an inductor coupled to the variable capacitance device. 
 
     
     
       16. The digitally controlled oscillator of  claim 15 , further comprising:
 a third transistor coupled to the variable capacitance device and the inductor; and 
 a fourth transistor coupled to the third transistor, the third transistor being cross-coupled to the fourth transistor. 
 
     
     
       17. The digitally controlled oscillator of  claim 15 , further comprising a capacitor coupled to the variable capacitance device. 
     
     
       18. A method, comprising:
 forming a semiconductor well; 
 forming first and second transistors in the semiconductor well, the first transistor including a first control node being configured to receive a control signal, the second transistor including a second control node being configured to receive an inverse of the control signal; and 
 coupling the first and second transistors in parallel between first and second nodes. 
 
     
     
       19. The method of  claim 18 , further comprising coupling the second node to a supply voltage rail. 
     
     
       20. The method of  claim 18  wherein the
 semiconductor well is a p-type well and the first and second transistors are n-channel transistors, or the semiconductor well is an n-type well and the first and second transistors are p-channel transistors. 
 
     
     
       21. The method of  claim 18 , further comprising surrounding the semiconductor well with an isolation trench. 
     
     
       22. The method of  claim 18 , further comprising coupling an inverter between the first control node and the second control node, the inverter being configured to receive the control signal.