Method of manufacturing solid-state image sensor

Abstract

A solid-state image sensor is manufactured through a plurality of photolithography processes. The plurality of photolithography processes includes at least one first lithography process including a dividing exposure step of exposing a substrate using a plurality of photomasks, and at least one second lithography process including a non-dividing exposure step of exposing the substrate using one photomask. The at least one first lithography process includes a process for forming a resist pattern to define active regions on the substrate, and a process for forming a resist pattern to define charge accumulation region.

What is claimed is: 
     
       1. A method of manufacturing a solid-state image sensor through a plurality of photolithography processes,
 wherein the plurality of photolithography processes includes at least one first lithography process including a dividing exposure step of exposing a substrate using a plurality of photomasks, and at least one second lithography process including a non-dividing exposure step of exposing the substrate using one photomask, 
 the at least one first lithography process includes a process for forming a resist pattern to define active regions on the substrate, and a process for forming a resist pattern to define charge accumulation region. 
 
     
     
       2. The method according to  claim 1 , wherein the at least one first lithography process includes a process for forming a resist pattern to define semiconductor regions arranged on the charge accumulation regions, and
 a conductivity type of the semiconductor regions is different from a conductivity type of the charge accumulation regions. 
 
     
     
       3. The method according to  claim 1 , wherein the at least one first lithography process includes a process for forming a resist pattern to define potential barrier regions arranged between neighboring charge accumulation regions, and a conductivity type of the potential barrier regions is different from a conductivity type of the charge accumulation regions. 
     
     
       4. The method according to  claim 1 , wherein the at least one first lithography process includes a process for forming a resist pattern to define channel stop regions arranged around element isolation regions. 
     
     
       5. The method according to  claim 1 , wherein the solid-state image sensor includes a pixel array portion and peripheral circuit portions, elements included in the pixel array portions are formed in a common well region, and the peripheral circuit portions are formed outside the well region, and
 the at least one second lithography process includes a process for forming a resist pattern to define the well region on the substrate. 
 
     
     
       6. The method according to  claim 1 , wherein the at least one second lithography process includes a process for forming a resist pattern to define a light-shielding pattern.