Multi-power mode reference clock with constant duty cycle

Abstract

A power management apparatus and method for maintaining a substantially constant duty cycle of a reference clock signal in a multi-power oscillator, includes a first output power transistor in electrical parallel with a series arrangement of a second output power transistor and a switch, and a crystal oscillator capacitively coupled to a common gate of the first and second output power transistors, wherein a level of the reference clock signal power output is a normal power level when the switch is open and the level of the reference clock signal power output is a higher power level when the switch is closed to operate the second output power transistor in parallel with the first output power transistor.

What is claimed is: 
     
       1. A power management apparatus for maintaining a substantially constant duty cycle of a reference clock signal in a multi-power oscillator, comprising:
 a first output power transistor in electrical parallel with a series arrangement of a second output power transistor and a switch; and 
 a crystal oscillator capacitively coupled to a common gate of the first and second output power transistors, wherein a level of the reference clock signal power output is a normal power level when the switch is open and the level of the reference clock signal power output is a higher power level when the switch is closed to operate the second output power transistor in parallel with the first output power transistor. 
 
     
     
       2. The apparatus of  claim 1 , wherein an output of the apparatus is a reference clock signal of a substantially fixed duty cycle in a normal power mode when the switch is open. 
     
     
       3. The apparatus of  claim 1 , wherein the output of the apparatus is a reference clock signal of the substantially same fixed duty cycle in a high power mode when the switch is closed. 
     
     
       4. The apparatus of  claim 1 , wherein the switch comprises an MOS switch. 
     
     
       5. The apparatus of  claim 1 , further comprising a bias device MOS transistor in parallel with the first and second output power transistors, wherein a gate of the bias device MOS transistor is coupled to the common gate of the first and second output power transistors. 
     
     
       6. The apparatus of  claim 5 , wherein the bias device MOS transistor comprises a fixed bias device and a one or more auxiliary bias devices in parallel, wherein each auxiliary bias device includes a series switch. 
     
     
       7. The apparatus of  claim 1 , wherein the duty cycle of the reference clock remains substantially constant to within ±0.1%. 
     
     
       8. A power management apparatus for maintaining a substantially constant duty cycle reference clock signal output, comprising:
 a first output device in electrical parallel with a series arrangement of a second output device and a switch; and 
 a frequency source device capacitively coupled to the first output device and the second output device, wherein a level of the reference clock signal power output is a normal power level when the switch is open and the level of the reference clock signal power output is a higher power level when the switch is closed to operate the second output power device in parallel with the first output power device. 
 
     
     
       9. The apparatus of  claim 8 , wherein an output of the apparatus is a reference clock signal of a substantially fixed duty cycle in a normal power mode when the switch is open. 
     
     
       10. The apparatus of  claim 8 , wherein the output of the apparatus is a reference clock signal of the substantially same fixed duty cycle in a high power mode when the switch is closed. 
     
     
       11. The apparatus of  claim 8 , wherein the switch comprises an MOS switch. 
     
     
       12. The apparatus of  claim 8 , further comprising a bias device in parallel with the first output device and the second output device, wherein the bias device is coupled to the first output device and the second output device. 
     
     
       13. The apparatus of  claim 12 , wherein the bias device comprises a fixed bias device and one or more auxiliary bias devices in parallel, wherein each auxiliary bias device includes a series switch. 
     
     
       14. The apparatus of  claim 8 , wherein the duty cycle of the reference clock signal remains substantially constant to within ±0.1%. 
     
     
       15. A method of maintaining a stable duty cycle reference clock signal in a multi-power oscillator power management circuit, comprising:
 providing an oscillator signal to a gate of a first power output transistor to output a reference clock signal at a first normal power level; 
 providing the oscillator signal to a gate of a second power output transistor in parallel with the first power output transistor, wherein a switch is in series with the second power output transistor; and 
 closing the switch to place the second power output transistor in operable electrical parallel with the first power output transistor to output the reference clock signal at a second power level such that the combined output power level is a higher power output level than the first power output transistor output level alone. 
 
     
     
       16. The method of  claim 15 , wherein the duty cycle of the reference clock signal is constant within ±0.1% at both normal and higher power levels.