Method of manufacturing semiconductor device

Abstract

A method of manufacturing a semiconductor device includes forming first and second gate lines over a semiconductor substrate, wherein each second gate line has a greater width than each of the first gate lines, forming a first insulating layer surrounding the top and side walls of the first and the second gate lines so that first air gaps are formed between the first and second gate lines and between the first gate lines, forming a first reaction region in the first insulating layer by diffusing an etchant to a depth less than a target depth from a surface of the first insulating layer, removing the first reaction region, forming second reaction regions in the first insulating layer by diffusing the etchant to the target depth from the surface of the first insulating layer, and removing the second reaction regions exposing a portion of each first and second gate lines.

What is claimed is: 
     
       1. A method of manufacturing a semiconductor device, comprising:
 forming first gate lines and second gate lines over a semiconductor substrate, wherein each of the second gate lines has a greater width than each of the first gate lines; 
 forming a first insulating layer surrounding top and side walls of the first and the second gate lines so that first air gaps are formed between the first and second gate lines adjacent to each other and between the first gate lines; 
 forming a first reaction region in the first insulating layer by diffusing an etchant to a depth less than a target depth from a surface of the first insulating layer; 
 removing the first reaction region; 
 forming second reaction regions in the first insulating layer by diffusing the etchant to the target depth from the surface of the first insulating layer; and 
 removing the second reaction regions so that a portion of each of the first and the second gate lines is exposed. 
 
     
     
       2. The method of  claim 1 , further comprising:
 siliciding the exposed regions of the first and the second gate lines after removing the second reaction region; and 
 forming a second insulating layer over an entire structure comprising the silicided first and second gate lines so that second air gaps are formed between the first and second gate lines adjacent to each other and between the first gate lines. 
 
     
     
       3. The method of  claim 1 , wherein the first insulating layer is a silicon oxide layer. 
     
     
       4. The method of  claim 1 , wherein the etchant is NH 4 F or NH 4 F.HF radical. 
     
     
       5. The method of  claim 4 , wherein the etchant is formed by reacting source gases, including NF 3  and NH 3 , with plasma. 
     
     
       6. The method of  claim 4 , wherein (NH 4 ) 2 SiF 6  of a solid state is generated in the first and the second reaction regions by reacting the etchant with the first insulating layer at a first temperature. 
     
     
       7. The method of  claim 6 , wherein removing the first and the second reaction regions comprises sublimating (NH 4 ) 2 SiF 6  of a solid state into SiF 4 , NH 3 , and HF of a gaseous state at a second temperature. 
     
     
       8. The method of  claim 1 , wherein a temperature when removing the first and the second reaction regions is higher than a temperature when forming the first and the second reaction regions. 
     
     
       9. The method of  claim 1 , wherein forming the first reaction region is performed until the first reaction region comes in contact with a top of the second gate lines. 
     
     
       10. The method of  claim 1 , wherein the first reaction region is formed so that a region of the first insulating layer not reacting with the etchant remains between the first air gaps and the first reaction region.