Method and apparatus for clockless conversion of time interval to digital word

Abstract

Method and apparatus for detecting the beginning and end of a time interval using the control module and in mapping this time interval to a portion of electric charge proportional to this time interval and accumulated in the sampling capacitor and then realizing the process of charge redistribution in the array of redistribution by changing states of signals from relevant control outputs and in assignment of relevant values to bits in the digital word by means of the control module. After detection of the beginning of the next time interval, the charge is accumulated in the additional sampling capacitor and then the process of charge redistribution is realized and relevant values are assigned to bits of the digital word. When the beginning of the subsequent time interval is detected, the next cycle begins and electric charge is accumulated in the sampling capacitor again.

The invention claimed is: 
     
       1. A method for clockless conversion of time interval to digital word consisting in a detection of the beginning and of the end of the time interval by the use of the control module and in mapping this time interval to a portion of electric charge proportional to this time interval and delivered by the use of a current source while the portion of electric charge is accumulated in a sampling capacitor, or in the sampling capacitor and in a capacitor having the highest capacitance value in an array of redistribution, which is connected to the sampling capacitor in parallel, and then consisting in the realization of the process of accumulated electric charge redistribution in the array of redistribution in a known way by means of a control module by changes of states of signals from relevant control outputs, while the array of redistribution comprises an array of on-off switches, of change-over switches and of capacitors such that a capacitance value of each capacitor of a given index is twice as high as a capacitance value of a capacitor of a previous index, and also consisting in the assignment of relevant values to bits of the digital word by means of the control module characterized in that after termination of accumulation of electric charge in the sampling capacitor (C n ), or in the sampling capacitor (C n ) and in the capacitor (C n−1 ) having the highest capacitance value in the array of redistribution which is connected to the sampling capacitor (C n ) in parallel, and after detection of the beginning of the next time interval (T x+1 ) by means of the control module (CM), electric charge is delivered by the use of the current source and accumulated in the additional sampling capacitor (C nA ), and next the process of redistribution of electric charge accumulated in the additional sampling capacitor (C nA ) is realized and relevant values are assigned to bits (b n−1 , b n−2 , b 1 , b 0 ) in the digital word by means of the control module (CM) while accumulation of electric charge in the additional sampling capacitor (C nA ) and the process of redistribution of electric charge accumulated in the additional sampling capacitor (C nA ) and assignment of relevant values to bits (b n−1 , b n−2 , b 1 , b 0 ) in the digital word are realized such as for the sampling capacitor (C n ). 
     
     
       2. The method for conversion as claimed in  claim 1  characterized in that after termination of accumulation of electric charge in the additional sampling capacitor (C nA ) and after detection of the beginning of the subsequent time interval (T x+2 ) by means of the control module (CM), the next cycle begins and electric charge is delivered by the use of the current source and accumulated again in the sampling capacitor (C n ), or in the sampling capacitor (C n ) and in the capacitor (C n−1 ) having the highest capacitance value in the array of redistribution which is connected to the sampling capacitor (C n ) in parallel. 
     
     
       3. The method for conversion as claimed in  claim 1  characterized in that in a period of time when electric charge is delivered by the use of the current source and accumulated in the additional sampling capacitor (C nA ), a part of electric charge is accumulated simultaneously in the additional capacitor (C n−1A ) having the highest capacitance value in the array of redistribution which is connected to the additional sampling capacitor (C nA ) in parallel while a capacitance value of the additional capacitor (C n−1A ) having the highest capacitance value in the array of redistribution equals the capacitance value of the capacitor (C n−1A ) having the highest capacitance value in the array of redistribution. 
     
     
       4. The method for conversion as claimed in  claim 1  characterized in that after termination of process of redistribution, the charge, accumulated in the last of capacitors on which the reference voltage (U L ) had not been reached when the process of redistribution was realized, is conserved. 
     
     
       5. An apparatus for clockless conversion of time interval to digital word comprising an array of redistribution whose control inputs are connected to control outputs of a control module and the control module is equipped with a digital output, a complete conversion output, a time interval signal input InT, a first control input connected to an output of a first comparator and a second control input connected to an output of a second comparator whereas a source of auxiliary voltage, a section of the sampling capacitor and a second controlled current source are connected to the array of redistribution while a control input of the second controlled current source is connected to an output controlling the second current source and the one end of the second current source is connected to a source rail and the other end of the second current source is connected to a destination rail and a voltage supply is connected to the one end of the first current source whose control input is connected to an output controlling the first current source whereas the array of redistribution comprises sections whose number equals a number of bits in the digital word, and a section of the sampling capacitor and each section of the array of redistribution comprises a source on-off switch, a destination on-off switch, a ground change-over switch and at least one capacitor whose top plate is connected to the source rail through the source on-off switch and/or to the destination rail through the destination on-off switch and whose bottom plate is connected to ground of the circuit or to the source of auxiliary voltage through the ground change-over switch while a capacitance value of each capacitor of a given index in the array of redistribution is twice as high as a capacitance value of a capacitor of a previous index and also the destination rail is connected to ground of the circuit through the destination on-off switch and to a non-inverting input of a second comparator whose inverting input is connected to the source of a reference voltage and the source rail is connected to an inverting input of a first comparator whose non-inverting input is connected to the source of auxiliary voltage whereas control inputs of the source on-off switches and a control input of the destination rail on-off switch are connected appropriately to the control outputs of the control module and control inputs of the destination on-off switches are coupled together and connected appropriately to the control outputs of the control module characterized in that the other end of the first current source (I) is connected to the section of the sampling capacitor (A n ) comprising the additional sampling capacitor (C nA ), the top plate change-over switches (S Tn , S TnA ), the bottom plate change-over switches (S Bn , S BnA ) while the top plate of the sampling capacitor (C n ) and the top plate of the additional sampling capacitor (C n−1 ) are connected to the source on-off switch (S Hn ) and to the destination on-off switch (S Ln ) or to the other end of the first current source (I) through the top plate change-over switches (S Tn , S TnA ) whereas the bottom plate of the sampling capacitor (C n ) and the bottom plate of the additional sampling capacitor (C nA ) are connected to the ground change-over switches (S Gn ) or to ground of the circuit through the bottom plate change-over switches (S Bn , S BnA ) and the control inputs of the top plate change-over switches (S Tn , S TnA ) and the control inputs of the bottom plate change-over switches (S Bn , S BnA ) are coupled together and connected appropriately to the output controlling the change-over switches of the plates (A C ). 
     
     
       6. The apparatus for conversion as claimed in  claim 5  characterized in that at least one section in the array of redistribution (A) comprises the additional capacitor (C n−1A , C n−2A , . . . , C 1A , C 0A ), the top plate change-over switches (S Tn−1 , S Tn−2 , . . . , S T1 , S T0 ; S Tn−1A , S Tn−2A , . . . , S T1A , S T0A ) and the bottom plate change-over switches (S Bn−1 , S Bn−2 , . . . , S B1 , S B0 ; S Bn−1A , S Bn−2A , . . . , S B1A , S B0A ) while the top plates of the capacitors (C n−1 , C n−2 , . . . , C 1 , C 0 ) and the top plates of the additional capacitors (C n−1A , C n−2A , . . . , C 1A , C 0A ) are connected appropriately to the source on-off switches (S Hn−1 , S Hn−2 , . . . , S H1 , S H0 ) and to the destination on-off switches (S Ln−1 , S Ln−2 , . . . , S L1 , S L0 ) or to the other end of the first current source (I) through the top plate change-over switches (S Tn−1 , S Tn−2 , . . . , S T1 , S T0 ; S Tn−1A , S Tn−2A , . . . , S T1A , S T0A ) whereas the bottom plates of the capacitors (C n−1 , C n−2 , . . . , C 1 , C 0 ) and the bottom plates of the additional capacitors (C n−1A , C n−2A , . . . , C 1A , C 0A ) are connected appropriately to the ground change-over switches (S Gn−1 , S Gn−2 , . . . , S G1 , S G0 ) or to ground of the circuit through the bottom plate change-over switches (S Bn−1 , S Bn−2 , . . . , S B1 , S B0 ; S Bn−1A , S Bn−2A , . . . , S B1A , S B0A ) whereas the control inputs of the top plate change-over switches (S Tn−1 , S Tn−2 , . . . , S T1 , S T0 ; S Tn−1A , S Tn−2A , . . . , S T1A , S T0A ) and the control inputs of the bottom plate change-over switches (S Bn−1 , S Bn−2 , . . . , S B1 , S B0 ; S Bn−1A , S Bn−2A , . . . , S B1A , S B0A ) are coupled together and connected to the output controlling the change-over switches of the plates (A C ). 
     
     
       7. The apparatus for conversion as claimed in  claim 6  characterized in that the capacitance value of the sampling capacitor (C n ) and the capacitance value of the additional sampling capacitor (C nA ) are not lower than the capacitance value of the capacitor (C n−1 ) having the highest capacitance value in the array of redistribution. 
     
     
       8. The apparatus for conversion as claimed in  claim 6  characterized in that the capacitance value of the additional capacitor (C n−1A , C n−2A , . . . , C 1A , C 0A ) in the array of redistribution is equal appropriately to the capacitance value of the capacitor (C n−1 , C n−2 , . . . , C 1 , C 0 ) in the array of redistribution.