US8741742B2ActiveUtilityA1
Method of fabricating an integrated circuit without ground contact pad
Est. expiryJun 9, 2031(~4.8 yrs left)· nominal 20-yr term from priority
Inventors:François Tailliet
H10W 90/756H10W 72/5473H10W 72/5449H10W 72/932H10W 70/421H10P 74/273H01L 22/32
44
PatentIndex Score
0
Cited by
13
References
4
Claims
Abstract
The disclosure relates to a method of fabricating an integrated circuit of CMOS technology in a semiconductor wafer comprising scribe lines. According to the disclosure, a ground contact pad of the integrated circuit is made in a scribe line of the wafer and is destroyed during a step of individualizing the integrated circuit by singulation of the wafer. A ground contact of the integrated circuit is made on the back side of the integrated circuit when it is assembled in an interconnection package.
Claims
exact text as granted — not AI-modifiedThe invention claimed is:
1. A method of fabricating an electronic device, comprising:
fabricating an integrated circuit, the fabricating including:
forming scribe lines in a semiconductor wafer,
embedding a circuit region in a substrate of the wafer,
making, on a front side of the wafer, a ground contact pad of the integrated circuit that is electrically linked to the circuit region and to the substrate, wherein the ground contact pad of the integrated circuit is made in one of the scribe lines of the wafer, and
individualizing the integrated circuit by singulating the wafer in the scribe lines and destroying the ground contact pad; and
assembling the integrated circuit in a package that includes a ground plane and interconnection leads, the assembling including electrically contacting a back side of the integrated circuit with a ground interconnection lead of the package and thereby replacing the ground contact pad destroyed during individualizing the integrated circuit.
2. A method according to claim 1 , wherein the ground interconnection lead forms a prolongation of the ground plane.
3. A method according to claim 1 , comprising electrically linking the ground interconnection lead to the ground plane of the package using a conductive element.
4. A method according to claim 1 , wherein the integrated circuit is a CMOS integrated circuit.Join the waitlist — get patent alerts
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