Performing reciprocal instructions with high accuracy

Abstract

In one embodiment, the present invention includes a method for receiving a reciprocal instruction and an operand in a processor, accessing an entry of a lookup table based on a portion of the operand and the instruction, generating an encoder output based on a type of the reciprocal instruction and whether the reciprocal instruction is a legacy instruction, and selecting portions of the lookup table entry and input operand to be provided to a reciprocal logic unit based on the encoder output. Other embodiments are described and claimed.

What is claimed is: 
     
       1. An apparatus comprising:
 a processor having an execution unit including a plurality of logic units to execute instructions, the execution unit including:
 a first selector to select a first portion or a second portion of an input operand based on whether an instruction is to perform a reciprocal operation or a square root reciprocal operation; 
 a lookup table coupled to the first selector and including a plurality of entries, wherein the output of the first selector is to access a given one of the plurality of entries, each of the entries including a first term, a second term, and a legacy portion, wherein the first and second terms are set at a midpoint of an interval; 
 a reciprocal logic unit including a plurality of levels of carry save adders (CSA) to receive the accessed entry and a portion of the input operand and to generate a reciprocal result for the input operand responsive to the instruction, wherein the first term is to be provided from the lookup table to a first level of the CSA adders; 
 an encoder to receive a selection signal from a second selector, the second selector to output a portion of the input operand if the instruction is a reciprocal instruction or a square root reciprocal instruction and is to output a first value instead if the instruction is a legacy instruction; and 
 
 wherein the legacy portion is used to generate a legacy result when the instruction is one of a legacy reciprocal instruction and a legacy square root reciprocal instruction. 
 
     
     
       2. The apparatus of  claim 1 , further comprising a third selector coupled to the second selector, wherein the third selector is to provide a first portion of the input operand to the second selector if the instruction is the reciprocal instruction and to provide a second portion of the input operand to the second selector if the instruction is the square root reciprocal instruction. 
     
     
       3. The apparatus of  claim 1 , wherein the legacy instruction is to provide a result having a lower relative accuracy than the reciprocal instruction or the square root reciprocal instruction. 
     
     
       4. The apparatus of  claim 3 , wherein the reciprocal instruction and the square root reciprocal instruction are to provide a relative accuracy of at least 2 −14 . 
     
     
       5. The apparatus of  claim 1 , further comprising a set of multiplexers controlled by an output of the encoder, wherein each of the set of multiplexers is to provide a partial product value to a first level of the CSA adders, the partial product value generated using the encoder output and a selected one of a plurality of inputs to the multiplexer, wherein the encoder output is to select the one of the plurality of inputs. 
     
     
       6. The apparatus of  claim 1 , further comprising a second level CSA adder coupled to receive an output of the first level of the CSA adders. 
     
     
       7. The apparatus of  claim 6 , further comprising a third level CSA adder coupled to receive an output of the second level CSA adder and a portion of the output of the first level of the CSA adders. 
     
     
       8. The apparatus of  claim 5 , wherein the legacy portion is to be provided to low order bits of a first one of the set of multiplexers to generate the legacy result. 
     
     
       9. The apparatus of  claim 1 , wherein each of the first terms of the entries is compensated by a correction value to provide a sign magnitude correction for the reciprocal logic unit. 
     
     
       10. The apparatus of  claim 9 , wherein the correction value is to zero out leading sign bits of the multiplexer outputs. 
     
     
       11. The apparatus of  claim 1 , wherein the reciprocal logic unit is to generate the reciprocal result in a single iteration. 
     
     
       12. A method comprising:
 receiving a reciprocal instruction and an input operand in a processor; 
 accessing an entry of a lookup table based on a portion of the input operand and the instruction, the lookup table including a plurality of entries, each of the entries including a first term, a second term, and a legacy portion, wherein the first and second terms are related to a midpoint of an interval; 
 generating an encoder output based on a type of the reciprocal instruction and whether the reciprocal instruction is a legacy instruction, wherein the encoder is to receive a selection signal from a second selector, the second selector to output a portion of the input operand if the reciprocal instruction is not a legacy instruction and to output a first value instead if the reciprocal instruction is a legacy instruction, wherein the legacy portion is used to generate a legacy result when the reciprocal instruction is one of a legacy reciprocal instruction and a legacy square root reciprocal instruction; and 
 selecting portions of the accessed lookup table entry and input operand to be provided to a reciprocal logic unit including a plurality of levels of carry save adders (CSA) to receive the accessed lookup table entry and a portion of the input operand and to generate a reciprocal result for the input operand responsive to the reciprocal instruction, wherein the first term is to be provided from the lookup table to a first level of the CSA adders based on the encoder output. 
 
     
     
       13. The method of  claim 12 , further comprising processing the selected portions in a Wallace tree structure of the reciprocal logic unit. 
     
     
       14. The method of  claim 13 , further comprising outputting a reciprocal value from the Wallace tree structure in a single iteration responsive to the reciprocal instruction. 
     
     
       15. A system comprising:
 a processor having a plurality of cores, each core including a front end to receive and decode instructions, an out-of-order (OOO) engine coupled to the front end to receive instructions, and an execution unit coupled to the OOO engine to receive and execute instructions, the execution unit including a first selector to select a first portion or a second portion of an input operand based on whether an instruction is to perform a reciprocal operation or a square root reciprocal operation, a lookup table coupled to the first selector and including a plurality of entries, wherein the output of the first selector is to access a given one of the plurality of entries, each of the entries including a first term, a second term, and a legacy portion, wherein the first and second terms are set at a midpoint of an interval, and a reciprocal logic unit including a plurality of levels of carry save adders (CSA) to receive the accessed entry and a portion of the input operand and to generate a reciprocal result for the input operand responsive to the instruction in a single iteration, wherein the first term is to be provided from the lookup table to a first level of the CSA adders and an encoder is to receive a selection signal from a second selector, the second selector to output a portion of the input operand if the instruction is a reciprocal instruction or a square root reciprocal instruction and to output a first value instead if the instruction is a legacy instruction, wherein the legacy portion is used to generate a legacy result when the instruction is one of a legacy reciprocal instruction and a legacy square root reciprocal instruction; and 
 a dynamic random access memory (DRAM) coupled to the processor. 
 
     
     
       16. The system of  claim 15 , further comprising a third selector coupled to the second selector, wherein the third selector is to provide a first portion of the input operand to the second selector if the instruction is the reciprocal instruction and to provide a second portion of the input operand to the second selector if the instruction is the square root reciprocal instruction.