Core circuit test architecture

Abstract

A scan test architecture facilitates low power testing of semiconductor circuits by selectively dividing the serial scan paths into shorter sections. Multiplexers between the sections control connecting the sections into longer or shorted paths. Select and enable signals control the operation of the scan path sections. The output of each scan path passes through a multiplexer to compare circuits on the semiconductor substrate. The compare circuits also receive expected data and mask data. The compare circuits provide a fail flag output from the semiconductor substrate.

What is claimed is: 
     
       1. An integrated circuit comprising:
 A. a substrate of semiconductor material; 
 B. functional core circuitry formed on the substrate, the functional core circuitry including functional flip-flops; 
 C. a stimulus input lead; 
 D. first and second scan paths formed on the substrate, each scan path having a stimulus input, connections with the functional core circuitry for communicating test patterns to and from the functional core circuitry, and a response output, each scan path including functional flip-flops of the functional core circuitry that, in a test mode, are connected in series, and the stimulus input of the first scan path being coupled to the stimulus input lead; and 
 E. first multiplexer circuitry having a first input coupled to the stimulus input lead, a second input connected to the response output of the first scan path, a control input, and an output connected to the stimulus input of the second scan path. 
 
     
     
       2. The integrated circuit of  claim 1  including:
 A. a third scan path having a stimulus input, connections with the functional core circuitry for communicating test patterns to and from the functional core circuitry, and a response output, the third scan path including functional flip-flops of the functional core circuitry that, in a test mode, are connected in series; and 
 B. second multiplexer circuitry having a first input coupled to the stimulus input lead, a second input connected to the response output of the second scan path, a control input, and an output connected to the stimulus input of the third scan path. 
 
     
     
       3. The integrated circuit of  claim 1  including output multiplexer circuitry having a first input coupled to the response output of the first scan path, a second input coupled to the response output of the second scan path, a control input, and an output.