Driver apparatus, print head, and image forming apparatus

Abstract

A driver apparatus drives light emitting elements connected to a common terminal. A clock driver outputs first and second pulses to first and second output terminals, respectively, alternately. A differentiating circuit includes an inductor and a resistor, and differentiates the first and second pulses to produce first and second clocks, respectively. A data driver circuit outputs a data signal to the common terminal in response to an ON/OFF command signal. A scanning circuit starts to operate in response to a starting signal such that the cascaded sub scanning stages turn on in sequence one at a time. A sub scanning stage turns on in response to the second clock, outputting a drive signal to a corresponding one of the light emitting elements. The light emitting elements emit light only when the drive signal and the ON/OFF command signal are fed to the light emitting elements.

What is claimed is: 
     
       1. A driver apparatus for driving a plurality of light emitting elements commonly connected to a common terminal, comprising:
 a clock driver configured to output a first clock pulse to a first output terminal and a second clock pulse to a second output terminal, the first clock pulse and the second clock pulse being produced based on a scanning square signal and outputted alternately; 
 a differentiating circuit formed of an inductor and a resistor, the differentiating circuit differentiating the first clock pulse thereby to produce a first clock and differentiating the second clock pulse to thereby produce a second clock, the first clock and the second clock each having a waveform that is produced by back electromotive force induced across the inductor; 
 a first clock terminal to which the first clock is outputted from the differentiating circuit; 
 a second clock terminal to which the second clock is outputted from the differentiating circuit; 
 a data driver circuit that outputs a data signal to the common terminal in response to an ON/OFF command signal; 
 a scanning circuit including a plurality of cascaded sub scanning stages which starts to operate in response to a starting signal such that the cascaded sub scanning stages turn on in sequence one at a time, the plurality of cascaded sub scanning stages having 
 an odd-numbered sub scanning stage that turns on in response to the first clock and outputs a drive signal to a corresponding one of the light emitting elements, and 
 an even-numbered sub scanning stage that turns on in response to the second clock and outputs a drive signal to a corresponding one of the light emitting elements, 
 wherein the light emitting elements emit light only when the drive signal and the ON/OFF command signal are fed to the light emitting elements. 
 
     
     
       2. The driver apparatus according to  claim 1 , wherein each odd-numbered sub scanning stage includes a three-terminal switch element, the three-terminal switch element including a first terminal connected to a first power supply for supplying a first power supply voltage, a second terminal connected to the first clock terminal, and a third terminal connected to a corresponding odd-numbered light emitting element; and
 wherein each even-numbered sub scanning stage includes a three-terminal switch element, the three-terminal switch element including a first terminal connected to the first power supply, a second terminal connected to the second clock terminal, and a third terminal connected to a corresponding even-numbered light emitting element. 
 
     
     
       3. The driver apparatus according to  claim 2 , wherein the scanning circuit comprises:
 a first diode having a cathode connected to a starting one of the sub scanning stages and having an anode to which the start signal is fed; and 
 a second diode having a cathode connected to a following one of adjacent sub scanning stages and an anode connected to a preceding one of the adjacent sub scanning stages, 
 wherein each of the third terminals is connected through a resistor to a second power supply for supplying a second power supply voltage less than the first power supply voltage. 
 
     
     
       4. The driver apparatus according to  claim 2 , wherein each of the third terminals is connected through a resistor to a second power supply for supplying a second power supply voltage less than the first power supply voltage. 
     
     
       5. The driver apparatus according to  claim 4 , wherein the clock driver includes a first buffer and a second buffer, wherein the first buffer includes;
 a first switch element connected between the first power supply and the first output terminal, and turning ON and OFF in response to the scanning square signal; 
 a second switch element connected between the second power supply and the first output terminal, and turning ON and OFF in response to the scanning square signal, wherein the first switch element and the second switch element alternately turn on and off such that when one switches on and the other switches off, so that the first output terminal changes between a high logic level and a low logic level; and 
 a first diode in parallel with the second switch element, the first diode having an anode connected to the second power supply; 
 wherein the second buffer includes; 
 
       a third switch element connected between the first power supply and the second output terminal, and turning ON and OFF in response to the scanning square signal;
 a fourth switch element connected between the second power supply and the second output terminal and turning ON and OFF in response to the scanning square signal, wherein the third switch element and the fourth switch element alternately turn ON and OFF such that when one switches on, the other switches off, so that the second output terminal changes between a high logic level and a low logic level; and 
 a second diode in parallel with the fourth switch element, the second diode having an anode connected to the second power supply. 
 
     
     
       6. The driver apparatus according to  claim 5 , wherein the first switch element and the third switch element are formed of MOS transistors of a first conductivity type, and configured to switch ON and OFF in response to the scanning square signal;
 wherein the second switch element and the fourth switch element are formed of MOS transistors of a second conductivity type, and configured to switch ON and OFF in response to the scanning square signal; 
 wherein the first diode is a parasitic diode across the MOS transistor of the second switch element; and 
 wherein the second diode is a parasitic diode across the MOS transistor of the fourth switch element. 
 
     
     
       7. The driver apparatus according to  claim 4 , wherein the clock driver includes a first three-state buffer and a second three-state buffer, wherein the first three-state buffer includes;
 a first switch element connected between the first power supply and the first output terminal, and turning ON and OFF in response to the scanning square signal; 
 a second switch element connected between the second power supply and the first output terminal, and turning ON and OFF in response to the scanning square signal, the first switch element and the second switch element alternately turning ON and OFF such that when one switches on, the other switches off, so that the first output terminal changes among a high level, a low level, and a high-impedance state; and 
 a first diode in parallel with the second switch element, the first diode having an anode connected to the second power supply; 
 wherein the second three-state buffer includes; 
 a third switch element connected between the first power supply and the second output terminal and turning ON and OFF in response to the scanning square signal; 
 a fourth switch element connected between the second power supply and the second output terminal and turning ON and OFF in response to the scanning square signal, wherein the third switch element and the fourth switch element alternately turn on and off such that when one switches on, the other switches off, so that the second output terminal changes among a high logic level, a low logic level, and a high-impedance state; and 
 a second diode in parallel with the fourth switch element, the second diode having an anode connected to the second power supply. 
 
     
     
       8. The driver apparatus according to  claim 4 , wherein the resistor is a first resistor of a plurality of resistors, and the third terminal of sub scanning stages after a starting one of the sub scanning stages is connected to the second power supply through a second resistor. 
     
     
       9. The driver apparatus according to  claim 2 , wherein the differentiating circuit is connected between the first clock terminal and the second clock terminal. 
     
     
       10. The driver apparatus according to  claim 1 , wherein each odd-numbered sub scanning stage includes a three-terminal switch element, the three-terminal switch element including a first terminal connected to a first clock terminal, a second terminal connected to a second power supply for supplying a second power supply voltage, and a third terminal connected to a corresponding odd-numbered light emitting element; and
 wherein each even-numbered sub scanning stage includes a three-terminal switch element, the three-terminal switch element including a first terminal connected to the second clock terminal, a second terminal connected to the second power supply, and a third terminal connected to a corresponding even-numbered light emitting element. 
 
     
     
       11. The driver apparatus according to  claim 10 , wherein the scanning circuit comprises:
 a first diode having an anode connected to a starting one of the sub scanning stages and having a cathode to which the starting signal is fed; and 
 a second diode having a cathode connected to a preceding one of adjacent sub scanning stages and an anode connected to a following one of the adjacent sub scanning stages, 
 wherein each of the third terminals is connected through a resistor to a first power supply for supplying a first power supply voltage greater than the second power supply voltage. 
 
     
     
       12. The driver apparatus according to  claim 10 , wherein each of the third terminals is connected through a resistor to a first power supply for supplying a first power supply voltage greater than the second power supply voltage. 
     
     
       13. The driver apparatus according to  claim 12 , wherein the clock driver includes a first buffer and a second buffer, wherein the first buffer includes;
 a first switch element connected between the first power supply and the first output terminal, and turning ON and OFF in response to the scanning square signal; 
 a second switch element connected between the second power supply and the first output terminal, and turning ON and OFF in response to the scanning square signal, wherein the first switch element and the second switch element alternately turn on and off such that when one switches on, the other switches off, so that the first output terminal changes between a high logic level and a low logic level; and 
 a first diode in parallel with the second switch element, the first diode having an anode connected to the second power supply; 
 wherein the second buffer includes; 
 a third switch element connected between the first power supply and the second output terminal and turning ON and OFF in response to the scanning square signal; 
 a fourth switch element connected between the second power supply and the second output terminal and turning ON and OFF in response to the scanning square signal, wherein the third switch element and the fourth switch element alternately turn ON and OFF such that when one switches on, the other switches off, so that the second output terminal changes between a high logic level and a low logic level; and 
 a second diode in parallel with the fourth switch element, the second diode having an anode connected to the second power supply. 
 
     
     
       14. The driver apparatus according to  claim 13 , wherein the first switch element and the third switch element are formed of MOS transistors of a first conductivity type, and configured to switch ON and OFF in response to the scanning square signal;
 wherein the second switch element and the fourth switch element are formed of MOS transistors of a second conductivity type, and configured to switch ON and OFF in response to the scanning square signal; 
 wherein the first diode is a parasitic diode across the MOS transistor of the second switch element; and 
 wherein the second diode is a parasitic diode across the MOS transistor of the fourth switch element. 
 
     
     
       15. The driver apparatus according to  claim 12 , wherein the first clock terminal supplies a power supply voltage and the second power supply supplies a ground potential;
 wherein the clock driver includes a first three-state buffer and a second three-state buffer, wherein the first three-state buffer includes; 
 a first switch element connected between the first power supply and the first output terminal, and turning ON and OFF in response to the scanning square signal; 
 a second switch element connected between the second power supply and the first output terminal, and turning ON and OFF in response to the scanning square signal, the first switch element and the second switch element alternately turning ON and OFF such that when one switches on, the other switches off, so that the first output terminal changes among a high level, a low level, and a high-impedance state; and 
 a first diode in parallel with the second switch element, the first diode having an anode connected to the second power supply; 
 wherein the second three-state buffer includes; 
 a third switch element connected between the first power supply and the second output terminal and turning ON and OFF in response to the scanning square signal; 
 a fourth switch element connected between the second power supply and the second output terminal and turning ON and OFF in response to the scanning square signal, wherein the third switch element and the fourth switch element alternately turn on and off such that when one switches on, the other switches off, so that the second output terminal changes among a high logic level, a low logic level, and a high-impedance state; and 
 a second diode in parallel with the second switch element, the second diode having an anode connected to the second power supply. 
 
     
     
       16. The driver apparatus according to  claim 12 , wherein the resistor is a first resistor of a plurality of resistors, and the third terminal of a starting one of the sub scanning stages is connected to the first power supply through a second resistor. 
     
     
       17. The driver apparatus according to  claim 1 , wherein the starting signal is the second clock signal fed through a resistor. 
     
     
       18. The driver apparatus according to  claim 1  further comprising a circuit for generating the starting signal. 
     
     
       19. The driver apparatus according to  claim 18 , wherein the starting signal is fed from the circuit to a starting one of the sub scanning stages through a diode. 
     
     
       20. The driver apparatus according to  claim 1 , wherein the odd-numbered sub scanning stage is a thyristor and even-numbered sub scanning stage is a thyristor. 
     
     
       21. The driver apparatus according to  claim 1 , wherein the light emitting elements are three-terminal light emitting elements. 
     
     
       22. The driver apparatus according to  claim 1 , wherein the light emitting elements are light emitting thyristors. 
     
     
       23. The driver apparatus according to  claim 1 , wherein the light emitting elements are two-terminal light emitting elements. 
     
     
       24. The driver apparatus according to  claim 23 , wherein the two-terminal light emitting elements are light emitting diodes. 
     
     
       25. A print head incorporating the driver apparatus according to  claim 1  and light emitting elements according to  claim 1 . 
     
     
       26. An image forming apparatus incorporating the print head according to  claim 25 , comprising:
 a photoconductive body; and 
 a charging section that charges a surface of the photoconductive body; 
 wherein the print head illuminates the charge surface of the photoconductive body to form an electrostatic latent image on the photoconductive body. 
 
     
     
       27. The driver apparatus according to  claim 1 , wherein:
 the first output terminal and the second output terminal are connected to the first clock terminal and the second clock terminal, respectively; and 
 the inductor is connected between the first clock terminal and the second clock terminal. 
 
     
     
       28. The driver apparatus according to  claim 1 , wherein the waveform is either an overshoot waveform or an undershoot waveform.