Method and system for fault protection using a linear feedback shift register

Abstract

A method, system and apparatus for fault protection using a linear feedback shift register are presented. The system comprises a protected register containing a first portion for holding a value for a sequence of numbers and a second portion for other parameters. The system also comprises a linear feedback shift register circuit configured to write the sequence of numbers to the first portion of the protected register. If the written sequence of numbers of the protected register matches a reference sequence of numbers, a rewrite circuit is configured to write the second portion of the protected register.

What is claimed is: 
     
       1. A system for fault protection, the system comprising:
 a protected register comprising a first portion for holding a value for a sequence of numbers and a second portion for other parameters; 
 a linear feedback shift register circuit configured to write the sequence of numbers to the first portion of the protected register; and 
 a rewrite circuit configured to write the second portion of the protected register if the written sequence of numbers of the protected register matches a reference sequence of numbers. 
 
     
     
       2. The system of  claim 1 , further comprising:
 a reference register configured to provide the reference sequence of numbers. 
 
     
     
       3. The system of  claim 2 , wherein the reference register is implemented in hardware. 
     
     
       4. The system of  claim 1 , wherein the linear feedback shift register circuit comprises firmware for write access to the protected register. 
     
     
       5. The system of  claim 1 , wherein the rewrite circuit comprises firmware for write access to the protected register. 
     
     
       6. The system of  claim 1 , wherein the sequence of numbers is a linear feedback shift register sequence of 4-bit values. 
     
     
       7. The system of  claim 1 , wherein the second portion of the protected register contains a hardware parameter for a read laser power threshold in an optical drive. 
     
     
       8. The system of  claim 7 , further comprising:
 a circuit for shutting down the optical drive if a forward sense voltage exceeds the read laser power threshold. 
 
     
     
       9. A method for fault protection, comprising:
 performing a linear feedback shift register test using a protected register; and 
 writing at least one portion of the protected register if the linear feedback shift register test is successful, 
 wherein performing the linear feedback shift register test comprises:
 generating a sequence of numbers; 
 writing the generated sequence of numbers to the protected register; 
 providing a reference sequence of numbers; and 
 comparing the generated sequence of numbers with the reference sequence of numbers to determine whether the linear feedback shift register test is successful. 
 
 
     
     
       10. The method of  claim 9 , further comprising:
 initializing the reference sequence of numbers; and 
 storing the reference sequence of numbers in a reference register. 
 
     
     
       11. The method of  claim 9 , further comprising:
 using firmware to write the protected register. 
 
     
     
       12. The method of  claim 9 , wherein generating a sequence of numbers comprises:
 generating a linear feedback shift register sequence of 4-bit values. 
 
     
     
       13. The method of  claim 9 , wherein writing at least one portion of the protected register comprises:
 writing a hardware parameter for a read laser power threshold in an optical drive. 
 
     
     
       14. The method of  claim 13 , further comprising:
 shutting down the optical drive if a forward sense voltage exceeds the read laser power threshold.