Memory device and method for fabricating the same

Abstract

A method for forming a memory device includes: forming a tunnel insulation layer, a conductive layer for a floating gate electrode, a charge blocking layer and a conductive layer for a control gate electrode over a substrate; and selectively etching the conductive layer for the control gate electrode, the charge blocking layer and the conductive layer for the floating gate electrode, thereby forming a plurality of gate lines, a plurality of select lines and at least two dummy lines disposed in a gap region between adjacent select lines, wherein the gate lines, the select lines and the dummy lines together construct strings.

What is claimed is: 
     
       1. A method for fabricating a memory device, the method comprising:
 forming a tunnel insulation layer, a conductive layer for a floating gate electrode, a charge blocking layer and a conductive layer for a control gate electrode over a substrate; and 
 selectively etching the conductive layer for the control gate electrode, the charge blocking layer and the conductive layer for the floating gate electrode, thereby forming a plurality of gate lines, a plurality of select lines and at least two dummy lines disposed in a gap region between adjacent select lines, wherein the gate lines, the select lines and the dummy lines together construct strings. 
 
     
     
       2. The method of  claim 1 , further comprising:
 forming an insulation layer over the gate lines, the select lines and the dummy lines; 
 selectively etching the insulation layer to form a contact hole exposing the substrate under a gap region between adjacent dummy lines; and 
 filling the contact hole with a conductive layer to form a source line. 
 
     
     
       3. The method of  claim 2 , wherein forming the contact hole comprises:
 forming a photoresist pattern on the insulation layer, wherein the photoresist pattern has an opened portion to expose a portion of the insulation layer that corresponds to a region where the source line is to be formed; and 
 etching the insulation layer using the photoresist pattern as an etch barrier, thereby forming the contact hole. 
 
     
     
       4. The method of  claim 3 , wherein a width of the opened portion of the photoresist pattern is greater than a width of the gap region between the adjacent dummy lines. 
     
     
       5. The method of  claim 2 , wherein the dummy lines contact the source line, thereby reducing the resistance of the source line. 
     
     
       6. The method of  claim 1 , wherein the control gate electrode comprises one of a polysilicon layer, a tungsten layer, a metal silicide layer and a combination thereof. 
     
     
       7. The method of  claim 2 , wherein forming the insulation layer comprises:
 forming a spacer on sidewalls of the gate lines, the select lines and the dummy lines to fill the gap region between the adjacent dummy lines ; 
 forming an etch stop layer over the spacer; and 
 forming an inter-insulation layer over the etch stop layer. 
 
     
     
       8. The method of  claim 7 , wherein the spacer comprises an oxide layer and the etch stop layer comprises a nitride layer. 
     
     
       9. A method for fabricating a memory device, the method comprising:
 forming a plurality of gate lines, a plurality of select lines and two dummy lines on a substrate, the dummy lines being disposed in a gap region between adjacent select lines; 
 forming an insulation layer over the gate lines, the select lines and the dummy lines; 
 selectively etching the insulation layer to form a contact hole that exposes the substrate between the two dummy lines; and 
 filling the contact hole with a conductive layer to form a source line. 
 
     
     
       10. The method of  claim 9 , wherein forming the contact hole comprises:
 forming a photoresist pattern on the insulation layer, wherein the photoresist pattern has an opened portion to expose a portion of the insulation layer that corresponds to a region where the source line is to be formed; and 
 etching the insulation layer using the photoresist pattern as an etch barrier, thereby forming the contact hole. 
 
     
     
       11. The method of  claim 10 , wherein a width of the opened portion of the photoresist pattern is greater than a width of a gap region between the two dummy lines. 
     
     
       12. The method of  claim 9 , wherein the dummy lines contact the source line, thereby reducing the resistance of the source line. 
     
     
       13. The method of  claim 9 , wherein forming the insulation layer comprises:
 forming a spacer on sidewalls of the gate lines, the select lines and the dummy lines to fill a gap region between the dummy lines; 
 forming an etch stop layer over the spacer; and 
 forming an inter-insulation layer over the etch stop layer. 
 
     
     
       14. The method of  claim 13 , wherein the spacer comprises an oxide layer and the etch stop layer comprises a nitride layer.