Method and apparatus for broadband input matching with noise and non-linearity cancellation in power amplifiers

Abstract

A CMOS differential power amplifier having broadband input matching with Noise and Non-linearity Cancellation. The broadband input match is realized by using two “Diode-Connected” NFETs (i.e., N-type Field Effect Transistors). Resulting noise degradation is reduced by using a noise cancellation structure. By using the same structure the disclosed method and apparatus also achieves non-linearity cancellation.

1. A circuit comprising:
 a) a first diode connected field effect transistor (FET) having a source, drain and gate and a resistor coupled between the drain and gate, the gate receiving a signal from a positive signal source; 
 b) a second FET having a source, drain and gate, the gate of the second FET coupled to the gate of the first diode connected FET and the source of the second FET coupled to the source of the first diode connected FET; 
 c) a third FET having a source, drain and gate, the gate of the third FET being coupled to the drain of the first diode connected FET and the source of the third FET being coupled to the source of the first diode connected FET; 
 d) a first constant current source coupled between the drain of the first diode connected FET and a power source; 
 e) a load structure having at least a first, second and third terminal, the first terminal coupled to the drain of the third FET and the second terminal coupled to the power source; 
 f) a fourth FET having a drain, source and gate, the drain of the fourth FET being coupled to the third terminal of the load structure, the source of the fourth FET coupled to the source of the first FET; 
 g) a fifth FET having a drain, source and gate, the drain of the fifth FET coupled to the drain of the third FET and the source of the fifth FET coupled to the source of the first FET; 
 h) a sixth FET having a source, drain and gate, the source of the sixth FET coupled source of the first FET, the drain of the sixth FET coupled to the gate of the fourth FET, and the gate of the sixth FET coupled to the gate of the fifth FET, the gate of the sixth FET receiving a signal from a negative signal source; 
 i) a second constant current source having a first and second terminal, the first terminal of the second constant current source coupled to the drain of the sixth FET and the second terminal of the second constant current source coupled to the second terminal of the load structure; and 
 j) a resistor coupled between the gate of the sixth FET and the drain of the sixth FET.