US8314032B2ActiveUtilityA1
Semiconductor device and method for manufacturing the same
Est. expiryAug 21, 2029(~3.1 yrs left)· nominal 20-yr term from priority
H10D 30/031H10D 86/0231H10D 86/60H10D 30/6755
97
PatentIndex Score
45
Cited by
17
References
17
Claims
Abstract
A method for manufacturing a thin film transistor (TFT) through a process including back exposure, in which oxide semiconductor is used for a channel layer; using an electrode over a substrate as a mask, negative resist is exposed to light from the back of the substrate; the negative resist except its exposed part is removed; and an electrode is shaped by etching a conductive film using the exposed part as an etching mask.
Claims
exact text as granted — not AI-modified1. A method for manufacturing a semiconductor device, comprising the steps of:
forming, over a substrate, a source electrode and a drain electrode from a metal film and
a channel layer from oxide semiconductor;
forming a gate insulating film over the source electrode, the drain electrode, and the channel layer;
forming a conductive film over the gate insulating film
coating the conductive film with negative resist;
exposing the negative resist to light from a back of the substrate using the source electrode and the drain electrode as a mask;
removing the negative resist except for an exposed part of the negative resist;
forming a gate electrode by etching the conductive film using the exposed part as an etching mask;
forming a first interconnect from the metal film on the substrate together with the source electrode and the drain electrode;
exposing the negative resist to light from the back of the substrate using, as a mask, the first interconnect as well as the source electrode and the drain electrode;
exposing part of the negative resist just above the first interconnect to light from a front side of the substrate through a photo mask;
removing the negative resist except exposed part of the negative resist; and
forming a second interconnect together with the age electrode by etching the conductive film using the exposed part as an etching mask.
2. The method for manufacturing a semiconductor device according to claim 1 , further comprising:
forming a third interconnect in an area of division of the second interconnect just above the first interconnect to connect the area.
3. The method for manufacturing a semiconductor device according to claim 1 , wherein i rays of a mercury lamp are used as a light source for the back exposure.
4. The method for manufacturing a semiconductor device according to claim 1 , wherein the substrate is a plastic film.
5. The method for manufacturing a semiconductor device according to claim 1 , wherein the channel layer is made of Zn—O, In—O, Ga—O, Sn—O, In—Ga—Zn—O, Zn—Sn—O, In—Sn—O, In—Zn—O, Ga—Zn—O or In—Ga—O.
6. The method for manufacturing a semiconductor device according to claim 1 , wherein the gate insulating film is made of Si—O, Al—O or Si—N.
7. The method for manufacturing a semiconductor device according to claim 1 , wherein the conductive film is made of In—Sn—O, Al—Zn—O, or Sn—O.
8. The method for manufacturing a semiconductor device according to claim 1 ,
wherein the substrate, the channel layer, the gate insulating film, and the conductive film are transparent; and
wherein the metal film is opaque.
9. A method for manufacturing a semiconductor device, comprising the steps of:
forming a gate electrode from a metal film over a substrate;
forming a gate insulating film over the gate electrode and the substrate;
forming a channel layer from oxide semiconductor over the gate insulating film;
forming a conductive film over the channel layer;
coating the conductive film with negative resist;
exposing the negative resist to light from a back of the substrate using the gate electrode as a mask;
removing the negative resist except for an exposed part of the negative resist; and
forming a source electrode and a drain electrode by etching the conductive film using the exposed part as an etching mask;
forming a first interconnect from the metal film on the substrate together with the gate electrode;
exposing the negative resist to light from the back of the substrate using, as a mask, the first interconnect as well as the gate electrode;
exposing part of the negative resist just above the first interconnect to light from a front side of the substrate through a photo mask;
removing the negative resist except exposed part of the negative resist; and
forming a second interconnect together with the source electrode and the drain electrode by etching the conductive film using the exposed part as an etching mask.
10. The method for manufacturing a semiconductor device according to claim 9 , further comprising:
forming a third interconnect in an area of division of the second interconnect just above the first interconnect to connect the area.
11. The method for manufacturing a semiconductor device according to claim 9 , wherein i rays of a mercury lamp are used as a light source for the back exposure.
12. The method for manufacturing a semiconductor device according to claim 9 , wherein the substrate is a plastic film.
13. The method for manufacturing a semiconductor device according to claim 9 , wherein the channel layer is made of Zn—O, In—O, Ga—O, Sn—O, In—Ga—Zn—O, Zn—Sn—O, In—Sn—O, In—Zn—O, Ga—Zn—O or In—Ga—O.
14. The method for manufacturing a semiconductor device according to claim 9 , wherein the gate insulating film is made of Si—O, Al—O or Si—N.
15. The method for manufacturing a semiconductor device according to claim 9 , wherein the conductive film is made of In—Sn—O, Al—Zn—O, or Sn—O.
16. The method for manufacturing a semiconductor device according to claim 9 ,
wherein the substrate, the channel layer, the gate insulating film, and the conductive film are transparent; and
wherein the metal film is opaque.
17. A semiconductor device manufactured by:
forming, over a substrate, a source electrode and a drain electrode from a metal film and a channel layer from oxide semiconductor;
forming a gate insulating film over the source electrode, the drain electrode, and the channel layer;
forming a conductive film over the gate insulating film;
coating the conductive film with negative resist;
exposing the negative resist to light from a back of the substrate using the source electrode and the drain electrode as a mask;
removing the negative resist except for an exposed part of the negative resist;
forming a gate electrode by etching the conductive film using the exposed part as an etching mask;
forming a first interconnect from the metal film on the substrate together with the source electrode and the drain electrode;
exposing the negative resist to light from the back of the substrate using, as a mask, the first interconnect as well as the source electrode and the drain electrode;
exposing part of the negative resist just above the first interconnect to light from a front side of the substrate through a photo mask;
removing the negative resist except exposed part of the negative resist; and
forming a second interconnect together with the gate electrode by etching the conductive film using the exposed part as an etching mask.Join the waitlist — get patent alerts
Track US8314032B2 — get alerts on status changes and closely related new filings.
We store only your email — no account needed. See our privacy policy.