Semiconductor memory device and self refresh test method

Abstract

A semiconductor memory device includes a memory cell array that includes a plurality of memory cells, an SR timer that determines a cycle of self refresh of the memory cell, a refresh counter that generates an internal address signal of the memory cell which is a target of the self refresh, and a circuit that outputs a pulse active signal to continuously execute refresh operation in one cycle of the self refresh.

1. A semiconductor memory device comprising:
 a memory cell array that comprises a plurality of memory cells; 
 an SR timer that determines a cycle of self refresh of the memory cell; 
 a refresh counter that generates an internal address signal of the memory cell which is a target of the self refresh; 
 a circuit that outputs a pulse active signal to continuously execute refresh operation in one cycle of the self refresh; 
 a first address register that receives a first external address signal and generates a first address signal; and 
 an internal address selection test circuit that selects one of the first address register signal and the internal address signal from the refresh counter, and determines the different internal address of the memory cell which is the target of continuous refresh operation, 
 wherein the circuit continuously executes the refresh operation on a different internal address of the memory cell. 
 
     
     
       2. A semiconductor memory device comprising:
 a memory cell array that comprises a plurality of memory cells; 
 an SR timer that determines a cycle of self refresh of the memory cell; 
 a refresh counter that generates an internal address signal of the memory cell which is a target of the self refresh; and 
 a circuit that outputs a pulse active signal to continuously execute refresh operation in one cycle of the self refresh; and 
 wherein the circuit comprises: 
 a continuous pulse active test circuit that generates the pulse active signal to continuously executed refresh operation; and 
 a refresh counter test circuit that generates a refresh counter control signal to control the refresh counter based on the pulse active signal, 
 wherein the continuous pulse active test circuit comprises: 
 an active test circuit that generates an active pulse number signal to determine active pulse number from an active test signal externally input; and 
 a continuous active control circuit that generates the pulse active signal in accordance with the active pulse number signal output from the active test circuit. 
 
     
     
       3. A semiconductor memory device comprising:
 a memory cell array that comprises a plurality of memory cells; 
 an SR timer that determines a cycle of self refresh of the memory cell; 
 a refresh counter that generates an internal address signal of the memory cell which is a target of the self refresh; and 
 a circuit that outputs a pulse active signal to continuously execute refresh operation in one cycle of the self refresh; 
 wherein the circuit comprises: 
 a continuous pulse active test circuit that generates the pulse active signal to continuously execute refresh operation; and 
 a refresh counter test circuit that generates a refresh counter control signal to control the refresh counter based on the pulse active signal, and 
 wherein the refresh counter test circuit comprises: 
 an active number counter that counts the number of refresh operations in accordance with the pulse active signal; 
 an active judgment circuit that compares the number of refresh operations counted by the active number counter with the active pulse number in accordance with the active pulse number signal to judge whether to continuously perform the refresh operation; and 
 a logic circuit that outputs the refresh counter control signal to continuously perform the refresh operation when it is judged by the active judgment circuit that the number of refresh operations counted by the active number counter has not reached the active pulse number. 
 
     
     
       4. The semiconductor memory device according to  claim 2 , wherein the circuit continuously executes the refresh operation on the same internal address of the memory cell. 
     
     
       5. The semiconductor memory device according to  claim 2 , wherein the circuit continuously executes the refresh operation on a different internal address of the memory cell. 
     
     
       6. The semiconductor memory device according to  claim 3 , wherein the circuit continuously executes the refresh operation on the same internal address of the memory cell. 
     
     
       7. The semiconductor memory device according to  claim 3 , wherein the circuit continuously executes the refresh operation on a different internal address of the memory cell.