Fast level shifter

Abstract

Some of the embodiments of the present disclosure provide a method comprising providing an integrated circuit with a level shifting circuit having a pull up device that is configured to selectively pull up a voltage level of an output signal from a low voltage level to a high voltage level, and having a pull down device that is configured to selectively pull down the voltage level of the output signal from the high voltage level to the low voltage level; ascertaining a high level of an input control signal; and when the output signal is at the high voltage level, deasserting the pull up device. Other embodiments are also described and claimed.

1. A method comprising:
 providing an integrated circuit with a level shifting circuit having
 a pull up device coupled between a high voltage line and an output terminal, wherein the pull up device is configured to selectively pull up a voltage level of an output signal at the output terminal from a low voltage level to a high voltage level, 
 a chopper circuit comprising a delay logic and a gate circuit, wherein the chopper circuit is configured to (i) receive the output signal and an input control signal, (ii) generate a delayed version of the output signal using the delay logic, (iii) based on the delayed version of the output signal and the input control signal, generate a switching signal, and 
 a pull down device coupled between a low voltage line and the output terminal, wherein the pull down transistor is configured to selectively pull down the voltage level of the output signal from the high voltage level to the low voltage level; 
 
 ascertaining a high level of the input control signal; and 
 when the output signal is at the high voltage level, deasserting, based on the switching signal, the pull up device at an end of a delay period that starts in response to the output signal reaching the high voltage level. 
 
     
     
       2. The method of  claim 1 , further comprising:
 asserting the pull up device in response to ascertaining the high level of the input control signal, wherein asserting the pull up device causes the output signal to be pulled up from the low voltage level to the high voltage level, and 
 deasserting the pull up device at least after the output signal has stabilized at its high voltage level. 
 
     
     
       3. The method of  claim 1 , wherein the delay period is provided to allow sufficient time to stabilize the output signal at the high voltage level or to complete an assertion of a keeper circuit. 
     
     
       4. The method of  claim 1 , further comprising:
 ascertaining a low level of the input control signal; and 
 in response to ascertaining the low level of the input control signal, asserting the pull down device to cause the output signal to be pulled down from the high voltage level to the low voltage level. 
 
     
     
       5. The method of  claim 1 , further comprising:
 enabling a keeper circuit, based on output signal reaching the high voltage level, to maintain the output signal at the high voltage level when the pull up device is deasserted. 
 
     
     
       6. The method of  claim 5 , further comprising:
 in response to a drop in a voltage level of the output signal while the output signal is being maintained at the high voltage level, disabling the keeper device. 
 
     
     
       7. A level shifter comprising:
 a pull up transistor coupled between a high voltage line and an output terminal, wherein the pull up transistor is configured to be switched on in response to a transition of an input signal from a low level to a high level, wherein said switching on of the pull up transistor causes an output signal at the output terminal to be pulled up from a low voltage level to a high voltage level; 
 a chopper circuit comprising a delay logic and a gate circuit, wherein the chopper circuit is configured to (i) receive the output signal and the input signal, (ii) generate a delayed version of the output signal using the delay logic, (iii) based on the delayed version of the output signal and the input signal, generate a switching signal, and (iv) based on the switching signal, switch off the pull up transistor at an end of a delay period that starts in response to the output signal being pulled up to the high voltage level; and 
 a pull down transistor coupled between a low voltage line and the output terminal, wherein the pull down transistor is configured to be switched on in response to a transition of the input signal from the high level to the low level to cause the output signal to be pulled down from the high voltage level to the low voltage level. 
 
     
     
       8. The level shifter of  claim 7 , further comprising:
 a keeper transistor adapted to be switched on in response to the output signal being pulled up to the high voltage level. 
 
     
     
       9. The level shifter of  claim 8 , wherein the keeper transistor is further adapted to maintain the output signal at the high voltage level, from a time the pull up transistor is switched off until the pull down transistor is switched on. 
     
     
       10. The level shifter of  claim 8 , wherein the keeper transistor is further adapted to be switched off in response to a drop in the output signal while the output signal is being pulled down to the low voltage level. 
     
     
       11. The level shifter of  claim 7 , wherein the delay period is defined to allow sufficient time to stabilize the output signal at the high voltage level or to allow proper switching on of the keeper transistor. 
     
     
       12. The level shifter of  claim 7 , wherein the pull down transistor is switched on after switching off of the pull up transistor. 
     
     
       13. The level shifter of  claim 7 , wherein the gate circuit comprises:
 a logical NOR gate adapted to receive at least the delayed version of the output signal; and 
 a logical NAND gate adapted to (i) receive an output of the logical NOR gate and the input signal, and (ii) generate the switching signal. 
 
     
     
       14. The level shifter of  claim 8 , wherein the pull up transistor is a p-channel metal-oxide-semiconductor (PMOS) transistor, the pull down transistor is an re-channel metal-oxide-semiconductor (NMOS) transistor, and the keeper transistor is a PMOS transistor. 
     
     
       15. The level shifter of  claim 8 , further comprising:
 an inverter adapted to receive the output signal and to control a gate terminal of the keeper transistor. 
 
     
     
       16. The level shifter of  claim 7 , further comprising:
 an inverter adapted to receive the input signal and to control a gate terminal of the pull down transistor. 
 
     
     
       17. The level shifter of  claim 7 , further comprising:
 an isolation low transistor adapted to pull down the output signal from the high voltage level to the low voltage level in response to an isolation low signal; and 
 an isolation high transistor adapted to pull up the output signal from the low voltage level to the high voltage level in response to an isolation high signal. 
 
     
     
       18. A method of operating a level shifter, the method comprising:
 receiving an input signal that transitions from a low level to a high level at a first time; 
 in response to the transition of the input signal from the low level to the high level, switching on a pull up transistor at the first time, wherein said switching on the pull up transistor causes an output signal at an output terminal to be pulled up from a low voltage level to a high voltage level, wherein the pull up transistor is coupled between a high voltage line and the output terminal; 
 generating, by a delay logic included in a chopper circuit, a delayed version of the output signal, wherein the delayed version of the output signal is pulled up from the low voltage level to the high voltage level at a second time that occurs subsequent to the first time: 
 generating, by a gate circuit included in the chopper circuit, a switching signal based on the delayed version of the output signal; 
 based on the switching signal, switching off the pull up transistor at the second time; and 
 in response to a transition of the input signal from the high level to the low level at a third time that occurs subsequent to the second time, switching on a pull down transistor, wherein said switching on the pull down device causes the output signal to be pulled down from the high voltage level to the low voltage level, wherein the pull down transistor is coupled between a low voltage line and the output terminal. 
 
     
     
       19. The method of  claim 18 , further comprising:
 in response to the output signal being pulled up to the high voltage level, switching on a keeper transistor; and 
 maintaining, using the keeper transistor, the output signal at the high voltage level, from the second time until the third time. 
 
     
     
       20. The method of  claim 19 , further comprising:
 switching off the keeper transistor at around the third time.