Apparatus processing video stream

Abstract

An apparatus processing a video stream includes a CPU, a memory access controller reading stream data from an external memory, a buffer storing the stream data, and a hardware accelerator decoding the stream data. The hardware accelerator includes a plurality of decoders decoding the stream data in accordance with one of a plurality of different video coding standards.

1. An apparatus for processing a video stream, comprising:
 a Central Processing Unit (CPU); 
 a memory access controller reading stream data from an external memory under the control of the CPU; 
 a buffer storing the stream data; and 
 a hardware accelerator decoding the stream data stored in the buffer under the control of the CPU, 
 wherein the hardware accelerator comprises:
 a plurality of decoders, each one of the plurality of decoders being configured to decode the stream data in accordance with a corresponding one of a plurality of different video coding standards, and 
 a stream controller receiving the stream data from the buffer and providing shifted stream data having a predetermined size in response to a bit stream length indicated by the CPU and stream length information. 
 
 
     
     
       2. The apparatus of  claim 1 , wherein the CPU outputs a first selection signal to select one of the plurality of decoders. 
     
     
       3. The apparatus of  claim 2 , wherein the hardware accelerator comprises a first selector outputting decoded stream data from the selected one of the plurality of decoders in response to the first selection signal. 
     
     
       4. The apparatus of  claim 3 , wherein the hardware accelerator further comprises a first register storing the first selection signal. 
     
     
       5. The apparatus of  claim 3 , wherein the hardware accelerator further comprises a first output circuit providing stream length information to the selected one of the plurality of decoders in response to the first selection signal. 
     
     
       6. The apparatus of  claim 5 , wherein the hardware accelerator further comprises a coefficient accelerator decoding a coefficient associated with the stream data. 
     
     
       7. The apparatus of  claim 6 , wherein the coefficient accelerator comprises a plurality of coefficient decoders, each one of the plurality of coefficient decoders being configured to decode the stream data in accordance with a corresponding one of a plurality of different video coding standards. 
     
     
       8. The apparatus of  claim 7 , wherein the CPU outputs a second selection signal selecting one of the plurality of coefficient decoders. 
     
     
       9. The apparatus of  claim 8 , wherein the hardware accelerator further comprises a second selector outputting a decoded coefficient from the selected one of the plurality of coefficient decoders in response to the second selection signal. 
     
     
       10. The apparatus of  claim 9 , wherein the hardware accelerator further comprises a second register storing the second selection signal. 
     
     
       11. The apparatus of  claim 10 , wherein the hardware accelerator further comprises a second output circuit providing stream length information to the selected one of the plurality of coefficient decoders in response to the second selection signal. 
     
     
       12. An apparatus for processing a video stream, comprising:
 a Central Processing Unit (CPU); 
 a memory access controller reading stream data from an external memory under the control of the CPU; 
 a buffer storing the stream data; and 
 a hardware accelerator decoding the stream data stored in the buffer under the control of the CPU, 
 wherein the hardware accelerator comprises a plurality of decoders, each one of the plurality of decoders being configured to decode the stream data in accordance with a corresponding one of a plurality of different video coding standards, 
 wherein the CPU outputs a first selection signal to select one of the plurality of decoders, 
 wherein the hardware accelerator comprises a first selector outputting decoded stream data from the selected one of the plurality of decoders in response to the first selection signal, 
 wherein the hardware accelerator further comprises a first output circuit providing stream length information to the selected one of the plurality of decoders in response to the first selection signal, 
 wherein the hardware accelerator further comprises a coefficient accelerator decoding a coefficient associated with the stream data, 
 wherein the coefficient accelerator comprises a plurality of coefficient decoders, each one of the plurality of coefficient decoders being configured to decode the stream data in accordance with a corresponding one of a plurality of different video coding standards, 
 wherein the CPU outputs a second selection signal selecting one of the plurality of coefficient decoders, 
 wherein the hardware accelerator further comprises a second selector outputting a decoded coefficient from the selected one of the plurality of coefficient decoders in response to the second selection signal, 
 wherein the hardware accelerator further comprises a second register storing the second selection signal, 
 wherein the hardware accelerator further comprises a second output circuit providing stream length information to the selected one of the plurality of coefficient decoders in response to the second selection signal, and 
 wherein the hardware accelerator further comprises a stream controller receiving the stream data from the buffer and providing shifted stream data having a predetermined size in response to a bit stream length indicated by the CPU and stream length information provided from at least one of the first and second output circuits. 
 
     
     
       13. The apparatus of  claim 12 , wherein the shifted stream data is provided to the CPU, the plurality of decoders, and the plurality of coefficient decoders. 
     
     
       14. The apparatus of  claim 1 , further comprising a firmware memory storing firmware code for the CPU.