Semiconductor memory device and method of fabricating the same

Abstract

A semiconductor memory device and a method of fabricating the same which is suitable for fabrication of a non-volatile memory, such as an EEPROM, using a polysilicon-insulator-polysilicon (PIP) process. The semiconductor memory device includes isolation layers defining a tunneling region and a read transistor region of a semiconductor substrate, a lower polysilicon film formed on and/or over the tunneling region and the read transistor region, a dielectric film formed on and/or over the lower polysilicon film in the tunneling region, and an upper polysilicon film formed on and/or over the dielectric film.

1. A semiconductor memory device comprising:
 a semiconductor substrate; 
 an isolation layer formed in the semiconductor substrate to define a tunneling region and a read transistor region, wherein a part of an active region of the tunneling region is exposed beside the isolation layer; 
 a lower polysilicon film formed on and overlapped with the tunneling region and the read transistor region; 
 a dielectric film formed on a portion of the lower polysilicon film that overlaps the tunneling region; and 
 an upper polysilicon film formed on the dielectric film, 
 wherein both the upper polysilicon film and the lower polysilicon film overlap with the part of the active region of the tunneling region. 
 
     
     
       2. The semiconductor memory device of  claim 1 , further comprising:
 an N-type well formed in the tunneling region of the semiconductor substrate; and 
 a P-type well formed in the read transistor region of the semiconductor substrate and spaced apart from the N-type well. 
 
     
     
       3. The semiconductor memory device of  claim 1 , wherein the lower polysilicon film comprises a floating gate. 
     
     
       4. The semiconductor memory device of  claim 1 , wherein the dielectric film comprises as a capacitor. 
     
     
       5. The semiconductor memory device of  claim 1 , wherein the upper polysilicon film comprises a control gate. 
     
     
       6. A semiconductor memory device comprising:
 a semiconductor substrate; 
 a plurality of isolation layers formed in the semiconductor substrate defining a tunneling region and a read transistor region, wherein a part of an active region of the tunneling region is exposed beside the isolation layers; 
 a first well formed in the tunneling region of the semiconductor substrate; 
 a second well formed in the read transistor region and spaced apart from the first well; 
 a first insulating film pattern formed on the first well in the tunneling region of the semiconductor substrate; 
 a second insulating film pattern formed on the second well in the read transistor region of the semiconductor substrate; 
 a floating gate formed on and contacting the isolation layers and overlapping the tunneling region and the read transistor region; 
 a dielectric film formed on a portion of the floating gate that overlaps the tunneling region; and 
 a control gate formed on the dielectric film, 
 wherein both the control gate and the floating gate overlap with the part of the active region of the tunneling region. 
 
     
     
       7. The semiconductor memory device of  claim 6 , wherein the first well comprises an N-type well and the second well comprises a P-type well. 
     
     
       8. The semiconductor memory device of  claim 6 , wherein the first insulating film pattern and the second insulating film pattern are respectively formed in a space between neighboring isolation patterns. 
     
     
       9. The semiconductor memory device of  claim 6 , further comprising:
 first spacers formed on sidewalls of the floating gate; and 
 second spacers formed on sidewalls of the control gate and the dielectric film. 
 
     
     
       10. A method of fabricating a semiconductor memory device comprising:
 forming a plurality of isolation layers in a semiconductor substrate to define a tunneling region and a read transistor region, wherein a part of an active region of the tunneling region is exposed beside the isolation layers; 
 forming a first well in the tunneling region of the semiconductor substrate; 
 forming a second well in the read transistor region of the semiconductor substrate, wherein the second well is spaced apart from the first well; 
 forming a first insulating film pattern on the first well in the tunneling region of the semiconductor substrate and a second insulating film pattern on the second well in the tunneling region of the semiconductor substrate; 
 forming a floating gate on and contacting the isolation layers and overlapping the tunneling region and the read transistor region; 
 forming a dielectric film on a portion of the floating gate that overlaps the tunneling region; 
 forming a control gate formed on the dielectric film, 
 wherein both the control gate and the floating gate overlap with the part of the active region of the tunneling region. 
 
     
     
       11. The method of  claim 10 , wherein the first well is formed by implanting N-type ions into the tunneling region. 
     
     
       12. The method of  claim 10 , wherein the second well is formed by implanting P-type ions into the read transistor region. 
     
     
       13. The method of  claim 10 , wherein forming the dielectric film comprises depositing an oxide film over the floating gate. 
     
     
       14. The method of  claim 10 , wherein forming the dielectric film comprises:
 depositing a first oxide film over the floating gate in the tunneling region of the semiconductor substrate; and then 
 depositing a nitride film over the first oxide film; and then 
 depositing a second oxide film over the nitride film; and then 
 patterning the first oxide film, the nitride film and the second oxide film. 
 
     
     
       15. The method of  claim 10 , wherein the dielectric film and the control gate are formed simultaneously. 
     
     
       16. The method of  claim 10 , further comprising, after forming the floating gate and before forming the dielectric film:
 forming first spacers formed on sidewalls of the floating gate. 
 
     
     
       17. The method of  claim 16 , further comprising, after forming the control gate:
 forming second spacers formed on sidewalls of the control gate and the dielectric layer. 
 
     
     
       18. The method of  claim 10 , wherein the isolation layers are formed through a local oxidation of silicon (LOCOS) process. 
     
     
       19. The method of  claim 10 , wherein the isolation layers are formed through a shallow trench isolation (STI) process.