Differential voltage defectivity monitoring method

Abstract

A method uses a differential voltage response to identify fabrication process defects that would result if an IC design is fabricated (without re-designing to correct such defects). The method uses two stacks, whose respective outputs may be compared by a comparator, and comparator's output used to determine defectivity. In some embodiments, each stack includes a first-type device (e.g. a p-channel device) and at least two second-type devices (e.g. n-channel devices). The first-type device is used as a current source or as a select switch (depending on the mode of operation of the differential voltage defectivity monitoring circuit). One second-type device may be used as a select switch and for back-bias control, while another second-type device may be used as a blocking switch and/or a select switch. The method may use an addressable array of multiple test structures that have digitally multiplexed control lines, in some embodiments.

1. A method of designing an integrated circuit (IC) in a wafer, the method comprising:
 simultaneously supplying power to each of a first stack having a plurality of first inputs coupled to a plurality of devices under test (DUTs) located within the wafer and a second stack having a plurality of second inputs coupled to a plurality of reference devices located within the wafer; 
 wherein each of the first stack and the second stack comprises a first-type device and at least two second-type devices; 
 wherein the first-type device is one of a p-channel device or an n-channel device; 
 wherein each second-type device is the other of the p-channel device or the n-channel device; 
 during said simultaneously supplying, comparing a first output from said DUTs and a second output from said reference device; 
 re-designing an existing IC design, based on at least an output resulting from said comparing; and 
 outputting a new IC design resulting from said re-designing. 
 
     
     
       2. The method of  claim 1  wherein:
 an identical voltage is supplied to each of the DUTs and the reference device during said simultaneously supplying. 
 
     
     
       3. The method of  claim 1  wherein:
 different voltages are supplied to each of the DUTs and the reference device during said simultaneously supplying. 
 
     
     
       4. The method of  claim 1  wherein:
 swept voltages are supplied to each of the DUTs and the reference device during said simultaneously supplying. 
 
     
     
       5. The method of  claim 1  wherein:
 different currents are supplied to each of the DUTs and the reference device during said simultaneously supplying. 
 
     
     
       6. The method of  claim 1  wherein:
 swept currents are supplied to each of the DUTs and the reference device during said simultaneously supplying. 
 
     
     
       7. The method of  claim 1  wherein:
 at least one characteristic of a device under test (DUT) in the first stack has a predetermined relationship with a corresponding characteristic of at least one reference device in the second stack. 
 
     
     
       8. A non-transitory computer-readable storage medium comprising data structures and software code to perform a method of designing an integrated circuit (IC) in a wafer, the software code comprising:
 computer instructions to simultaneously supply power to each of a first stack having a plurality of first inputs coupled to a plurality of devices under test (DUTs) located within the wafer and a second stack having a plurality of second inputs coupled to a plurality of reference devices located within the wafer; 
 wherein each of the first stack and the second stack comprising a first-type device and at least two second-type devices; 
 wherein the first-type device is one of a p-channel device or an n-channel device; 
 wherein each second-type device is the other of the p-channel device or the n-channel device; 
 wherein at least one characteristic of a device under test (DUT) in the first stack has a predetermined relationship with a corresponding characteristic of at least one reference device in the second stack; 
 computer instructions to compare a first output from said DUT and a second output from said reference device during execution of the computer instructions to simultaneously supply power; 
 computer instructions to re-design an existing IC design, based on at least an output resulting from execution of said computer instructions to compare; and 
 computer instructions to output a new IC design resulting from said re-designing. 
 
     
     
       9. The non-transitory computer-readable storage medium of  claim 8  wherein:
 an identical voltage is supplied to each of the DUTs and the reference device during execution of said computer instructions to simultaneously supply power. 
 
     
     
       10. The non-transitory computer-readable storage medium of  claim 8  wherein:
 different voltages are supplied to each of the DUTs and the reference device during execution of said computer instructions to simultaneously supply power. 
 
     
     
       11. The non-transitory computer-readable storage medium of  claim 8  wherein:
 swept voltages are supplied to each of the DUTs and the reference device during execution of said computer instructions to simultaneously supply power. 
 
     
     
       12. The non-transitory computer-readable storage medium of  claim 8  wherein:
 different currents are supplied to each of the DUTs and the reference device during execution of said computer instructions to simultaneously supply power. 
 
     
     
       13. The non-transitory computer-readable storage medium of  claim 8  wherein:
 swept currents are supplied to each of the DUTs and the reference device during execution of said computer instructions to simultaneously supply power.