Method and apparatus for controlling memory precharge operation

Abstract

A memory controller sequentially holds access requests including access addresses. A semiconductor memory includes a plurality of banks each having a plurality of pages. The memory controller decides page hit/page miss of the bank corresponding to each of the held access addresses. Further, the memory controller outputs an all-banks precharge command for performing a precharge operation of all the banks when deciding, based on an analysis of the successive access addresses, that outputting the all-banks precharge command results in improvement in access efficiency. It is possible to precharge the plural banks only by supplying the all-banks precharge command once, and therefore, in a case where the number of empty cycles for the insertion of a command is small, it is possible to supply the command efficiently to the semiconductor memory according to the states of the banks.

1. A memory controller accessing a semiconductor memory including a plurality of banks each having a plurality of pages, the memory controller comprising:
 a request hold unit sequentially holding access requests which include access addresses each indicating a group of memory cells to be accessed and which are supplied from a system controller; and 
 an address analysis unit receiving the access addresses held in the request hold unit to decide page hit/page miss of each of the banks corresponding to the access addresses, finding scores corresponding to the banks indicated by the access addresses, the scores each indicating access efficiency according to an all-banks precharge command for performing a precharge operation of all the banks, and outputting the all-banks precharge command when deciding, based on a sum of the scores, that outputting the all-banks precharge command results in improvement in the access efficiency. 
 
     
     
       2. The memory controller according to  claim 1 , wherein
 when a state of a page of a bank corresponding to a head access address among the access addresses held in the request hold unit is a page miss, the address analysis unit decides whether to output the all-banks precharge command, according to he sum of the scores corresponding to second and subsequent access addresses. 
 
     
     
       3. The memory controller according to  claim 2 , wherein
 the address analysis unit finds the scores for the second and subsequent access addresses respectively, each of the scores indicating whether or not outputting the all-banks precharge command results in a decrease in the number of cycles necessary for accessing and each of the scores being relatively large when the number of cycles decreases, and the address analysis unit outputs the all-banks precharge command when the sum of the scores exceeds a preset standard value. 
 
     
     
       4. The memory controller according to  claim 3 , further comprising
 a score memory unit programmably storing the scores corresponding to states of the banks, wherein 
 the address analysis unit refers to the scores stored in the score memory unit to compare the sum of the scores with the standard value. 
 
     
     
       5. The memory controller according to  claim 2 , wherein
 the address analysis unit outputs the all-banks precharge command prior to an activate command of the bank corresponding to the head access address. 
 
     
     
       6. The memory controller according to  claim 2 , wherein
 the address analysis unit outputs a precharge command for performing the precharge operation of one of the banks corresponding to the head access address when deciding not to output the all-banks precharge command. 
 
     
     
       7. The memory controller according to  claim 1 , wherein
 after outputting the all-banks precharge command, when an empty cycle in which a command is insertable exists between an activate command and one of a read and write command corresponding to each of the access addresses, the address analysis unit outputs a different activate command in correspondence to the empty cycle in order to activate at least one of idle banks corresponding to the second and subsequent access addresses. 
 
     
     
       8. A control method for accessing a semiconductor memory including a plurality of banks each having a plurality of pages, the method comprising:
 sequentially holding access requests which include access addresses each indicating a group of memory cells to be accessed and which are supplied from a system controller; 
 deciding page hit/page miss of each of the banks corresponding to the held access addresses; 
 finding scores corresponding to the banks indicated by the access addresses, the scores each indicating access efficiency according to an all-banks precharge command for performing a precharge operation of all the banks; and outputting the all-banks precharge command when deciding, based on a sum of the scores, that outputting the all-banks precharge command results in improvement in the access efficiency. 
 
     
     
       9. The control method for accessing the semiconductor memory according to  claim 8 , wherein
 when a state of a page of a bank corresponding to a head access address among the held access addresses is a page miss, it is decided whether to output the all-banks precharge command, according to the sum of the scores corresponding to second and subsequent access addresses. 
 
     
     
       10. The control method for accessing the semiconductor memory according to  claim 9 , wherein:
 the scores are found for the second and subsequent access addresses respectively, each of the scores indicating whether or not outputting the all-banks precharge command results in a decrease in the number of cycles necessary for accessing and each of the scores being relatively large when the number of cycles decreases, and 
 the all-banks precharge command is output when the sum of the scores exceeds a preset standard value. 
 
     
     
       11. The control method for accessing the semiconductor memory according to  claim 9 , wherein
 the all-banks precharge command is output prior to an activate command of the bank corresponding to the head access address. 
 
     
     
       12. The control method for accessing the semiconductor memory according to  claim 9 , wherein
 a precharge command for performing the precharge operation of one of the banks corresponding to the head access address is output when it is decided not to output the all-banks precharge command. 
 
     
     
       13. The control method for accessing the semiconductor memory according to  claim 8 , wherein
 after outputting the all-banks precharge command, when an empty cycle in which a command is insertable exists between an activate command and one of a read and write command corresponding to each of the access addresses, a different activate command is output in correspondence to the empty cycle in order to activate at least one of idle banks corresponding to the second and subsequent access addresses. 
 
     
     
       14. A system having a semiconductor memory including a plurality of banks each having a plurality of pages, at least one system controller outputting access requests for accessing the semiconductor memory and a memory controller outputting the access requests to the semiconductor memory, wherein
 the memory controller comprises: 
 a request hold unit sequentially holding the access requests which include access addresses each indicating a group of memory cells to be accessed and which are supplied from the system controller; and 
 an address analysis unit receiving the access addresses held in the request hold unit to decide page hit/page miss of each of the banks corresponding to the access addresses, finding scores corresponding to the banks indicated by the access addresses, the scores each indicating access efficiency according to an all-banks precharge command for performing a precharge operation of all the banks, and outputting the all-banks precharge command when deciding, based on a sum of the scores, that outputting the all-banks precharge command results in improvement in the access efficiency. 
 
     
     
       15. The system according to  claim 14 , wherein
 when a state of a page of a bank corresponding to a head access address among the access addresses held in the request hold unit is a page miss, the address analysis unit decides whether to output the all-banks precharge command, according to the sum of the scores corresponding to second and subsequent access addresses. 
 
     
     
       16. The system according to  claim 15 , wherein
 the address analysis unit finds the scores for the second and subsequent access addresses respectively, each of the scores indicating whether or not outputting the all-banks precharge command results in a decrease in the number of cycles necessary for accessing and each of the scores being relatively large when the number of cycles decreases, and the address analysis unit outputs the all-banks precharge command when the sum of the scores exceeds a preset standard value. 
 
     
     
       17. The system according to  claim 16 , further comprising
 a score memory unit programmably storing the scores corresponding to states of the banks, wherein 
 the address analysis unit refers to the scores stored in the score memory unit to compare the sum of the scores with the standard value. 
 
     
     
       18. The system according to  claim 15 , wherein
 the address analysis unit outputs the all-banks precharge command prior to an activate command of the bank corresponding to the head access address. 
 
     
     
       19. The system according to  claim 15 , wherein
 the address analysis unit outputs a precharge command for performing the precharge operation of one of the banks corresponding to the head access address when deciding not to output the all-banks precharge command. 
 
     
     
       20. The system according to  claim 14 , wherein
 after outputting the all-banks precharge command, when an empty cycle in which a command is insertable exists between an activate command and one of a read and write command corresponding to each of the access addresses, the address analysis unit outputs a different activate command in correspondence to the empty cycle in order to activate at least one of idle banks corresponding to the second and subsequent access addresses.