Semiconductor device including cross-coupled transistors formed from linear-shaped gate level features

Abstract

A semiconductor device includes first and second p-type diffusion regions, and first and second n-type diffusion regions that are each electrically connected to a common node. Each of a number of conductive features within a gate electrode level region is fabricated from a respective originating rectangular-shaped layout feature having a centerline aligned parallel to a first direction. The conductive features respectively form gate electrodes of first and second PMOS transistor devices, and first and second NMOS transistor devices. Gate electrodes of the first PMOS and second NMOS transistor devices are electrically connected in part by a first conductor within a first interconnect level. Gate electrodes of the second PMOS and first NMOS transistor devices are electrically connected in part by a second conductor within the first interconnect level. The first PMOS, second PMOS, first NMOS, and second NMOS transistor devices define a cross-coupled transistor configuration having commonly oriented gate electrodes.

1. A semiconductor device, comprising:
 a first transistor of a first transistor type defined by a first gate electrode and a first diffusion region of a first diffusion type electrically connected to a common diffusion node; 
 a first transistor of a second transistor type defined by a second gate electrode and a first diffusion region of a second diffusion type electrically connected to the common diffusion node; 
 a second transistor of the first transistor type defined by a third gate electrode and a second diffusion region of the first diffusion type electrically connected to the common diffusion node; 
 a second transistor of the second transistor type defined by a fourth gate electrode and a second diffusion region of the second diffusion type electrically connected to the common diffusion node, 
 wherein the first and fourth gate electrodes are electrically connected to each other, 
 wherein the second and third gate electrodes are electrically connected to each other, 
 wherein the first gate electrode is a portion of a first linear-shaped gate level feature, wherein the second gate electrode is a portion of a second linear-shaped gate level feature, wherein the third gate electrode is a portion of a third linear-shaped gate level feature, wherein the fourth gate electrode is a portion of a fourth linear-shaped gate level feature, 
 wherein each of the first, second, third, and fourth linear-shaped gate level features extends lengthwise in a first direction and is physically separate from another gate level feature, and 
 wherein the first and second diffusion regions of the first diffusion type are physically separated from each of the first and second diffusion regions of the second diffusion type. 
 
     
     
       2. A semiconductor device as recited in  claim 1 , further comprising:
 a third transistor of the first transistor type defined by a fifth gate electrode and a third diffusion region of the first diffusion type; and 
 a third transistor of the second transistor type defined by a sixth gate electrode and a third diffusion region of the second diffusion type, 
 wherein the fifth and sixth gate electrodes are electrically connected, 
 wherein the third transistor of the first transistor type is electrically connected in a serial manner to the first transistor of the first transistor type, and 
 wherein the third transistor of the second transistor type is electrically connected in a serial manner to the first transistor of the second transistor type. 
 
     
     
       3. A semiconductor device as recited in  claim 2 , wherein the fifth and sixth gate electrodes correspond to respective portions of a fifth linear-shaped gate level feature defined to extend lengthwise in the first direction. 
     
     
       4. A semiconductor device as recited in  claim 2 , further comprising:
 a fourth transistor of the first transistor type defined by a seventh gate electrode and a fourth diffusion region of the first diffusion type; and 
 a fourth transistor of the second transistor type defined by an eighth gate electrode and a fourth diffusion region of the second diffusion type, 
 wherein the seventh and eighth gate electrodes are electrically connected, 
 wherein the fourth transistor of the first transistor type is electrically connected in a serial manner to the second transistor of the first transistor type, and 
 wherein the fourth transistor of the second transistor type is electrically connected in a serial manner to the second transistor of the second transistor type. 
 
     
     
       5. A semiconductor device as recited in  claim 4 , wherein the seventh and eighth gate electrodes correspond to respective portions of a sixth linear-shaped gate level feature defined to extend lengthwise in the first direction. 
     
     
       6. A semiconductor device as recited in  claim 1 , further comprising:
 a fifth linear-shaped gate level feature defined to extend lengthwise in the first direction between the first and third gate electrodes. 
 
     
     
       7. A semiconductor device as recited in  claim 6 , wherein the fifth linear-shaped gate level feature includes a first portion that forms a gate electrode of a third transistor of the first transistor type. 
     
     
       8. A semiconductor device as recited in  claim 7 , wherein the third transistor of the first transistor type is electrically connected in a serial manner to both the first and second transistors of the first transistor type. 
     
     
       9. A semiconductor device as recited in  claim 7 , wherein the fifth linear-shaped gate level feature is also defined to extend lengthwise in the first direction between the second and fourth gate electrodes. 
     
     
       10. A semiconductor device as recited in  claim 9 , wherein the fifth linear-shaped gate level feature includes a second portion that forms a gate electrode of a third transistor of the second transistor type. 
     
     
       11. A semiconductor device as recited in  claim 10 , wherein the third transistor of the second transistor type is electrically connected in a serial manner to both the first and second transistors of the second transistor type. 
     
     
       12. A semiconductor device as recited in  claim 11 , wherein the third transistor of the first transistor type is electrically connected in a serial manner to both the first and second transistors of the first transistor type. 
     
     
       13. A semiconductor device as recited in  claim 1 , wherein the first and second diffusion regions of the first diffusion type are physically separate from each other. 
     
     
       14. A semiconductor device as recited in  claim 13 , wherein the first and second diffusion regions of the second diffusion type are physically separate from each other. 
     
     
       15. A semiconductor device, comprising:
 a first transistor of a first transistor type defined by a first gate electrode and a first diffusion region of a first diffusion type electrically connected to a common diffusion node; 
 a first transistor of a second transistor type defined by a second gate electrode and a first diffusion region of a second diffusion type electrically connected to the common diffusion node; 
 a second transistor of the first transistor type defined by a third gate electrode and a second diffusion region of the first diffusion type electrically connected to the common diffusion node; 
 a second transistor of the second transistor type defined by a fourth gate electrode and a second diffusion region of the second diffusion type electrically connected to the common diffusion node, 
 wherein the first and fourth gate electrodes are electrically connected to each other, 
 wherein the second and third gate electrodes are electrically connected to each other, 
 wherein each of the first, second, third, and fourth gate electrodes corresponds to a portion of an associated gate level feature defined within a corresponding gate level feature layout channel, 
 wherein each gate level feature is defined within its gate level feature layout channel without physically contacting another gate level feature defined within an adjoining gate level feature layout channel, 
 wherein the first and second diffusion regions of the first diffusion type are physically separated from each of the first and second diffusion regions of the second diffusion type, and 
 wherein the first gate electrode and either the second or fourth gate electrode are defined to extend lengthwise along a common line of extent in a first direction. 
 
     
     
       16. A semiconductor device as recited in  claim 15 , wherein the first gate electrode and the second gate electrode are defined to extend lengthwise along the common line of extent in the first direction, and
 wherein the third gate electrode and the fourth gate electrode extend lengthwise along different lines of extent in the first direction. 
 
     
     
       17. A semiconductor device as recited in  claim 15 , wherein the first gate electrode and the second gate electrode are defined to extend lengthwise along the common line of extent in the first direction, and
 wherein the third gate electrode and the fourth gate electrode are defined to extend lengthwise along a second common line of extent in the first direction. 
 
     
     
       18. A semiconductor device as recited in  claim 15 , wherein the first gate electrode and the fourth gate electrode are defined to extend lengthwise along the common line of extent in the first direction, and
 wherein the second gate electrode and the third gate electrode extend lengthwise along different lines of extent in the first direction. 
 
     
     
       19. A semiconductor device as recited in  claim 15 , wherein the first gate electrode and the fourth gate electrode are defined to extend lengthwise along the common line of extent in the first direction, and
 wherein the second gate electrode and the third gate electrode are defined to extend lengthwise along a second common line of extent in the first direction. 
 
     
     
       20. A semiconductor device as recited in  claim 15 , wherein the first and second diffusion regions of the first diffusion type are physically separate from each other. 
     
     
       21. A semiconductor device as recited in  claim 20 , wherein the first and second diffusion regions of the second diffusion type are physically separate from each other. 
     
     
       22. A semiconductor device, comprising:
 a first transistor of a first transistor type defined by a first gate electrode and a first diffusion region of a first diffusion type electrically connected to a common diffusion node; 
 a first transistor of a second transistor type defined by a second gate electrode and a first diffusion region of a second diffusion type electrically connected to the common diffusion node; 
 a second transistor of the first transistor type defined by a third gate electrode and a second diffusion region of the first diffusion type electrically connected to the common diffusion node; 
 a second transistor of the second transistor type defined by a fourth gate electrode and a second diffusion region of the second diffusion type electrically connected to the common diffusion node, 
 wherein the first and fourth gate electrodes are electrically connected to each other, 
 wherein the second and third gate electrodes are electrically connected to each other, 
 wherein each of the first, second, third, and fourth gate electrodes corresponds to a portion of an associated gate level feature defined within a corresponding gate level feature layout channel, 
 wherein each gate level feature is defined within its gate level feature layout channel without physically contacting another gate level feature defined within an adjoining gate level feature layout channel, 
 wherein the first and second diffusion regions of the first diffusion type are physically separated from each of the first and second diffusion regions of the second diffusion type, and 
 wherein each of the first, second, third, and fourth gate electrodes is defined to extend lengthwise in a first direction, and wherein a first centerline-to-centerline distance as measured in a second direction perpendicular to the first direction between the first and third gate electrodes is substantially equal to a first integer multiple of a fixed pitch distance, and wherein a second centerline-to-centerline distance as measured in the second direction between the second and fourth gate electrodes is substantially equal to a second integer multiple of the fixed pitch distance. 
 
     
     
       23. A semiconductor device as recited in  claim 22 , wherein the first integer multiple of the fixed pitch distance is greater than or equal to zero, and wherein the second integer multiple of the fixed pitch distance is greater than or equal to zero. 
     
     
       24. A semiconductor device as recited in  claim 22 , wherein the first integer multiple of the fixed pitch distance is equal to the second integer multiple of the fixed pitch distance. 
     
     
       25. A semiconductor device as recited in  claim 22 , wherein the first integer multiple of the fixed pitch distance is different from the second integer multiple of the fixed pitch distance. 
     
     
       26. A semiconductor device as recited in  claim 22 , wherein the second integer multiple of the fixed pitch distance is twice the first integer multiple of the fixed pitch distance. 
     
     
       27. A semiconductor device as recited in  claim 22 , wherein the second integer multiple of the fixed pitch distance is more than twice the first integer multiple of the fixed pitch distance. 
     
     
       28. A semiconductor device as recited in  claim 22 , wherein the first and second diffusion regions of the first diffusion type are physically separate from each other. 
     
     
       29. A semiconductor device as recited in  claim 28 , wherein the first and second diffusion regions of the second diffusion type are physically separate from each other.