US8035095B2ActiveUtilityA1

Resistive random access memory device

Assignee: SAMSUNG ELECTRONICS CO LTDPriority: Aug 24, 2007Filed: Jan 4, 2008Granted: Oct 11, 2011
Est. expiryAug 24, 2027(~1.1 yrs left)· nominal 20-yr term from priority
H10D 64/691G11C 2213/51G11C 13/0007G11C 2213/79G11C 2213/32
76
PatentIndex Score
6
Cited by
6
References
8
Claims

Abstract

Provided is a resistive random access memory device that includes a storage node connected to a switching device. The resistive random access memory device includes a first electrode, a resistance variable layer, and a second electrode which are sequentially stacked, wherein a diffusion blocking layer is formed between the first electrode and the resistance variable layer or between the resistance variable layer or/and the second electrode.

Claims

exact text as granted — not AI-modified
1. A resistive random access memory device, comprising:
 a switching device; 
 a storage node connected to the switching device, the storage node including a first electrode, a resistance variable layer, and a second electrode which are sequentially stacked; and 
 a diffusion blocking layer, including a boron nitride layer, between the first electrode and the resistance variable layer or between the resistance variable layer and the second electrode, 
 wherein the resistance variable layer is a transition metal oxide layer adapted to change resistance according to a voltage applied to the resistance variable layer. 
 
     
     
       2. The resistive random access memory device of  claim 1 , wherein the diffusion blocking layer has a bonding energy greater than that of the resistance variable layer. 
     
     
       3. The resistive random access memory device of  claim 1 , wherein the transition metal oxide layer is formed of one selected from the group consisting of a nickel oxide layer, a titanium oxide layer, a zirconium oxide layer, a zinc oxide layer, and a copper oxide layer. 
     
     
       4. The resistive random access memory device of  claim 1 , wherein the first electrode and the second electrode are platinum (Pt) layers. 
     
     
       5. The resistive random access memory device of  claim 1 , wherein the diffusion blocking layer has a thickness T of 0<T≦50 Å. 
     
     
       6. The resistive random access memory device of  claim 1 , wherein the diffusion blocking layer is between the first electrode and the resistance variable layer and between the resistance variable layer and the second electrode. 
     
     
       7. A resistive random access memory device, comprising:
 a switching device and a storage node connected to the switching device, the storage node including a first electrode, a resistance variable layer and a second electrode, sequentially stacked; and 
 a diffusion blocking layer, including a boron nitride layer, between the first electrode and the resistance variable layer or between the resistance variable layer and the second electrode, 
 wherein the resistance variable layer includes a transition metal oxide, and 
 at least one of the first electrode and the second electrode is a platinum (Pt) layer. 
 
     
     
       8. The resistive random access memory device of  claim 7 , wherein the diffusion blocking layer is between the first electrode and the resistance variable layer and between the resistance variable layer and the second electrode.

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