Memory cell having a side electrode contact

Abstract

Memory cells are described along with methods for manufacturing. A memory cell as described herein includes a bottom electrode, a memory element and a side electrode. The bottom electrode contacts the memory element at a first contact surface on the bottom of the memory element. The side electrode contacts the memory element at a second contact surface on the side of the memory element, where the second contact surface on the side faces laterally relative to the first contact surface on the bottom.

1. A memory device comprising:
 a bottom electrode having a width and a top surface; 
 an access line having a via extending there through such that the access line completely surrounds a perimeter of the via, the via overlying the bottom electrode and having a width greater than the width of the bottom electrode, the via having an inner surface; and 
 a memory element within the via, the memory element having a bottom surface in contact with the top surface of the bottom electrode, and having an outer surface surrounded by and in contact with the inner surface of the via. 
 
     
     
       2. The memory device of  claim 1 , wherein an inter-electrode current path between the bottom electrode and the access line turns laterally within the memory element relative to the direction of current flow at the top surface of the bottom electrode. 
     
     
       3. The memory device of  claim 1 , wherein:
 the memory element includes a base portion and an annular portion on the base portion, the base portion having a bottom surface extending the width of the via and in contact with the top surface of the bottom electrode, and the annular portion having an outer surface surrounded by and in contact with the inner surface of the via, and the annular portion having an inner surface defining an interior within the via; and further comprising: 
 a fill material within the interior defined by the inner surface of annular portion. 
 
     
     
       4. The memory device of  claim 3 , wherein the fill material comprises a dielectric material. 
     
     
       5. The memory device of  claim 3 , wherein the base portion has a thickness between the bottom surface and a top surface, through which current is confined in an inter-electrode current path. 
     
     
       6. The memory device of  claim 1 , wherein the memory element has an active region adjacent the top surface of the bottom electrode. 
     
     
       7. The memory device of  claim 1 , wherein a first contact area between the memory element and the bottom electrode is less than a second contact area between the memory element and the access line. 
     
     
       8. The memory device of  claim 1 , wherein the inner surface of the via is cylindrical, such that an inter-electrode current path spreads radially outward from the top surface of the bottom electrode to the inner surface of the via. 
     
     
       9. The memory device of  claim 1 , further comprising a fill layer having a top surface, and wherein:
 the bottom electrode extends to the top surface of the fill layer; and 
 the access line is on the top surface of the fill layer. 
 
     
     
       10. The memory device of  claim 1 , wherein the access line comprises a first conductive material contacting the memory element at the inner surface of the via, and a second conductive material separated from the memory element by the first material, the second material having a lower electrical resistivity than that of the first material. 
     
     
       11. A memory device comprising: a conductive contact having a top surface; a conductive line over the conductive contact; a via through the conductive line such that the conductive line completely surrounds a perimeter of the via, and the via having a bottom area, wherein the top surface of the conductive contact is in the bottom area of the via; and
 a cup-shaped memory element within the via and coupled to the conductive contact and the conductive line, the memory element having an outer surface surrounded by an inner surface of the via. 
 
     
     
       12. A memory device comprising:
 a bit line having a via, such that the bit line completely surrounds a perimeter of the via, the via having a width and an inner surface; 
 a bottom electrode under the via and having a width, the width of the via larger than the width of the bottom electrode; 
 and a concave memory element having a base portion and a sidewall portion within the via, the base portion coupled to the bottom electrode and the sidewall portion is coupled with the bit line, and the sidewall portion of the memory element has an outer surface surrounded by the inner surface of the via.